\section{Introduction}
\label{ch1:1}
-Traditionally, most of the software applications are structured as sequential programs, according to the Von Neumann report in 1993 \cite{ref50}. The structure of the program code is understandable by the human brain as a series of instructions that executed one after the other. For many years until a short time,
-with each new generation of microprocessors the users of the sequential applications have believed that these applications run faster over them.
-Nowadays, this idea is no longer valid because the recent releases of the microprocessors have many computing units embedded in one chip and these programs are only run over one computing unit sequentially.
-Consequently, traditional applications have not improved their performance a lot over the new architectures, whereas the new applications run faster over them in a parallel. The parallel application is executed over all available computing units at the same time to improve its performance. Furthermore, the concurrency revolution has been referred to the drastic improvement in the performance of new applications side by side to new parallel architectures \cite{ref51}. Therefore, parallel applications and parallel architectures are closely tied together. It is hard to think about any of parallel applications without thinking of the parallel hardware executed them.
-For example, the energy consumption of a parallel system mainly depends on both of the parallel applications and the parallel architectures execute these applications. Indeed, an energy consumption model or any measurement system depends on many specifications, some of them are concerning parallel hardware features such as the frequency of the processor, the power consumption of the processor and the communication model. The others are concerned the parallel application such as the computation and communication times of the application.
-
-In this work, the iterative parallel applications are interested and running them over different parallel architectures to optimize their energy consumptions is the main goal.
-As a result, this chapter is aimed to give a brief overview of parallel hardware architectures, parallel iterative applications and an energy model from the other authors used to measure the energy consumption of these applications.
-The reminder of this chapter is organized as follows: section \ref{ch1:2} is devoted
-to describing types of parallelism and types of parallel platforms. It also gives some information about parallel programming models. Section \ref{ch1:3} explains both of a synchronous and asynchronous parallel iterative methods and comparing them. Section \ref{ch1:4}, presents a well accepted energy model from the state of the art that can be used to measure the energy consumption of parallel iterative applications when changing the frequency of the processor. Finally, section \ref{ch1:5} summaries this chapter.
+
+Referred to the state of the art, specifically Von Neumann report in 1993 \cite{ref50}, most of the software applications are structured as sequential programs.
+The structure of the program code is understandable by the human brain as a series of instructions that
+are executed successively one after the other. For many years until a short time,
+with each new generation of microprocessors, users of sequential applications have believed that these applications must run faster than previous ones.
+Nowadays, this idea is no longer valid since recent releases of microprocessors have many computing units that are embedded in one chip and programs are running only over one computing unit sequentially.
+Indeed, new applications have significantly improved their performance over new architectures in parallel compared to traditional applications.
+In this context, the aim of improving the performance of parallel applications is executed simultaneously over all available computing units.
+ Furthermore, the concurrency revolution has been referred to the drastic improvement in the performance of new applications side by side to new parallel architectures \cite{ref51}. Therefore, parallel applications and parallel architectures are closely tied together.
+Moreover, thinking about parallel applications is directly related to think about parallel hardware that must support them.
+For example, the energy consumption of one parallel system mainly depends on both: (1) parallel applications and (2) parallel architectures. Indeed, an energy consumption model or any measurement system depends on many specifications, some of them are related to the parallel hardware features such as: (1) the frequency of processor, (2) the power consumption of processor and (3) the communication model. Others are relied to the parallel application such as: (1) the computation time and (2) the communication time of the application.
+
+
+This work is focused on studying the iterative parallel applications, where different parallel architectures
+are used to run them in parallel, which is considered as ultimate goal to optimize their energy consumptions.
+
+In this context, this chapter gives a brief overview about parallel hardware architectures and parallel iterative applications. Also, it discusses an energy model proposed by other authors used to measure the energy consumption of these applications.
+The reminder of this chapter is organized as follows: section \ref{ch1:2} describes different types of parallelism and different types of parallel platforms. It also explains some models of parallel programming. Section \ref{ch1:3} discusses both types of parallel iterative methods, synchronous and asynchronous one and comparing them. Section \ref{ch1:4}, presents a well accepted energy model from the state of the art that can be used to measure the energy consumption of parallel iterative applications when the frequency of processor is changed. Finally, section \ref{ch1:5} summarizes this chapter.
\section{Parallel Computing Architectures}
\label{ch1:2}
-The process of the simultaneous execution of calculations is called the parallel computing.
-Its main principle refers to the ability of dividing the large problem into smaller sub-problems that can be solved at the same time \cite{ref2}.
-Mainly, solving sub-problems of the main problem in a parallel computing are carried out on multiple parallel processors.
-Indeed, the parallel processor architecture is a computer system composed of many processing elements connected via network model in addition to software tools required to make the processing units work together \cite{ref1}.
-Consequently, the parallel computing architecture consists of a software and hardware resources.
-Hardware resources are processing units and the memory model in addition to the network system connecting them. Software resources include the specific operating system, the programming language and the compiler, or the runtime libraries. Furthermore, the parallel computing can have different levels of parallelism that can be performed in a software or a hardware level. There are five types of parallelism as follows:
+The process of executing the calculations simultaneously is called parallel computing.
+Its main principle refers to the ability of dividing a large problem into a smaller sub-problems that can be solved at the same time \cite{ref2}.
+Mainly, solving sub-problems of one main problem in parallel computing is carried out on multiple parallel processors.
+Indeed, parallel processor architecture can be defined as a computer system that is composed of many processing elements,
+which are connected via network model in addition to software tools that are required to make the processing units work together \cite{ref1}.
+In other words, the parallel computing architecture consists of a software and hardware resources.
+Hardware resources are: (1) the processing units, (2) the memory model and (3) the network system that is used to connect them. Software resources include (1) the specific operating system, (2) the programming language and (3) the compile or the runtime libraries. Besides, parallel computing may have different levels of parallelism that can be performed in a software or a hardware level. In this context, five types of parallelism levels have been defined as follows:
\begin{itemize}
-\item \textbf{Bit-level parallelism (BLP)}: The appearance of the very-large-scale integration (VLSI) in 1970s has been considered the first step towards the parallel computing. It is used to increase the number of bits in the word size being processed by a processor as in the figure~\ref{fig:ch1:1}. For many successive years, the number of bits have increased starting from 4 bit microprocessors reaching until 64 bit microprocessors. For example, the recent x86-64 architecture becomes the most familiar architecture nowadays. Therefore, the biggest word size gives more parallelism level and thus less instructions to be executed by a processor at the same time.
+\item \textbf{Bit-level parallelism (BLP)}: The appearance of very-large-scale integration (VLSI) in 1970s has been viewed as the first step towards parallel computing. It is used to increase the number of bits in the word size which is processed by a processor as illustrated in the figure~\ref{fig:ch1:1}. For many successive years, the number of bits have been increased starting from 4 bit to 64 bit microprocessors. For example nowadays, recent x86-64 architecture becomes the most familiar architecture. Noting that, the biggest word size is the more parallelism level. Thus, it reflects to less instructions to be executed by a processor.
\begin{figure}[h!]
\centering
\label{fig:ch1:1}
\end{figure}
-\item \textbf{Data-level parallelism (DLP)}: Data parallelism is a process of distributing the data vector between different parallel processors and each one performs the same operations on its data sub-vector. Therefore, many arithmetic operations can be performed on the same data vector in a simultaneous manner. This type of parallelism can be used in many programs, especially from the area of scientific computing. Usually, data-parallel operations are only provided for arrays operations, for example, see figure \ref{fig:ch1:2}. As an example about the applications use this type of parallelism are vector multiplication, image and signal processing.
+\item \textbf{Data-level parallelism (DLP)}: Data parallelism is the process of distributing data vector between different parallel processors, where each one performs the same operations on its data sub-vector. Therefore, many arithmetic operations can be performed on the same data vector in a simultaneous manner. This type of parallelism can be used in many programs, especially in the area of scientific computing. Usually, data-parallel operations are only provided to arrays operations, for example, as shown in figure \ref{fig:ch1:2}. Vector multiplication, image and signal processing can be considered as an example of applications that use this type of parallelism.
\begin{figure}[h!]
\centering
\label{fig:ch1:2}
\end{figure}
-\item \textbf{Instruction-level parallelism (ILP)}: Generally, the sequential program composed of many instructions. These instructions can be executed in a parallel at the same time, if each of them is independent from the others. In particular, the parallelism can be achieved in the instruction level by using a pipeline. It means all the independent instructions of the program are overlapped the execution of each others. For example, if we have two instructions $I_1$ and $I_2$, they are independent if there is no control and data dependency between them.
-In pipeline stages, the execution of each instruction is divided into multiple steps that can be overlapped with the steps of other instructions by the pipeline hardware unit.
-Figure~\ref{fig:ch1:3} demonstrates four instructions each one has four steps denoted as fetch, decode, execute and write, which are implemented in hardware units by pipeline.
+
+\item \textbf{Instruction-level parallelism (ILP)}: Generally, a sequential program is composed of many instructions. These instructions can be executed in parallel at the same time, if each of them is independent from others. In particular, the parallelism can be achieved in instruction level by using a pipeline. It means all independent instructions of a program are overlapped the execution of each others. For example, if we have two instructions: $I_1$ and $I_2$, they are independent if there is no control and no data dependency between them.
+In pipeline stages, the execution of each instruction is divided into multiple steps. Then, they can be overlapped with the steps of other instructions by a pipeline hardware unit.
+Figure~\ref{fig:ch1:3} demonstrates four instructions, where each one has four steps denoted as: (1) fetch, (2) decode, (3) execute and (4) write. Thus, they are implemented in hardware units by pipeline.
\begin{figure}[h!]
\centering
-\item \textbf{Thread-level parallelism (TLP)}: It is also known as a task-level parallelism.
-According to the Moore’s law \cite{ref9}, the processor can have number of transistors by a double
-each two years to increase the frequency of the processor and thus its performance. Besides, cache and main memory sizes are must increased together to satisfy this increased.
-But, this leads to some limits come from two main reasons, the first one is when the cache size is drastically increased leading to a larger access time. The second is related to the big increase in the number of the transistors per CPU that can be increased significantly the heat dissipation. As a result, programmers subdivided their programs into multiple tasks which can be executed in parallel over distributed processors or shared multi-cores processors to improve the performance of the program, see figure~\ref{fig:ch1:4}. Each processor can have a multiple or an individual thread dedicated for each task. A thread can be defined as a part of the parallel program which shares processor resources with other threads.
+\item \textbf{Thread-level parallelism (TLP)}: It is also known as task-level parallelism.
+According to Moore’s law \cite{ref9}, the processor can have a number of transistors
+that must doubled each two years to increase the frequency of processor, and consequently its improving
+performance. Besides, cache and main memory sizes must be increased together to response to this new change.
+However, this provides some issues: (1) the first issue is related to drastically increase in cache size, which leads to a large access time. (2) the second issue is related to the huge increase in the number of the transistors per CPU, which can increase significantly the heat dissipation. For that reasons, programmers subdivided their programs into multiple tasks which can be then executed in parallel over distributed processors or shared multi-cores processors to improve the performance, see figure~\ref{fig:ch1:4}. Each processor can have individual threads or multiple threads dedicated to each task. A thread can be defined as a part of the parallel program that shares processor resources with other threads.
\begin{figure}[h!]
\centering
\label{fig:ch1:4}
\end{figure}
-Therefore, we can consider the execution time of a sequential program composed of $N$ tasks as the sum of the execution times of all tasks as follows:
+Therefore, the execution time of a sequential program that is composed of $N$ tasks, is the sum of the execution times of all tasks. Thus, it is expressed as follows:
\begin{equation}
\label{ch1:eq1}
Sequential~execution~time = \sum_{i=1}^{N} T_i
\end{equation}
-Whereas, if tasks are executed synchronously over multiple processing units in a parallel, the execution time of the program is the execution time of the task that has maximum execution time (the slowest task) as follows:
+Whereas, if tasks are executed synchronously over multiple processing units in parallel, the execution time of the program is defined as the execution time of the task that has maximum execution time (the slowest task) as follows:
\begin{equation}
\label{ch1:eq2}
\end{equation}
\item \textbf{Loop-level parallelism (LLP)}:
-The numerical algorithms and many other algorithms are executed iteratively the same program portion, computation, using different forms of the loop statements allowed in the programming languages. At each iteration, the program need to scan a large data structure such as an array structure to make the arithmetic calculations. Inside the loop structure, there are many instructions that are independent or dependent. In a sequential loop execution the $i$ iteration must be executed after the completion of
+The numerical algorithms and many other algorithms are executed iteratively the same program portion, computations, using different forms of the loop statements that are allowed in the programming languages. At each iteration, the program needs to scan a large data structure such as array structure to perform the arithmetic calculations. Inside the loop structure, there are many instructions that are dependent or independent. In a sequential loop execution, the $i$ iteration must be executed after the completion of
$(i-1)$ iteration.
-Whereas, if each iteration is independent from the others, then all the iterations are distributed over many processors to be executed in a parallel
-for example, see figure\ref{fig:ch1:5}. In the parallel programming languages this type of a loop is called $parallel~loop$.
+Whereas, if each iteration is independent from others, then all iterations' instructions are distributed over many processors to be executed in parallel
+for example, see figure\ref{fig:ch1:5}. In the parallel programming languages, this type of loop is called $parallel~loop$.
\begin{figure}[h!]
\centering
-\includegraphics[scale=0.8]{fig/ch1/loop-para.pdf}
+\includegraphics[scale=0.85]{fig/ch1/loop-para.pdf}
\caption{Loop-level parallelism}
\label{fig:ch1:5}
\end{figure}
{N_{processors}}
\end{equation}
-For more detail about the levels of parallelism see \cite{ref3,ref4,ref6,ref7}.
+For more details about the levels of parallelism see \cite{ref3,ref4,ref6,ref7}.
\end{itemize}
\subsection{Types of Parallel platforms}
\label{ch1:2:1}
-The main goal behind using a parallel computer is to solve the bigger problem faster.
-A collection of processing elements composing them must to work together to perform the final solution of the main problem. However, many different architectures have been proposed
-and classified according to the parallelism in the instruction and data
-streams. In 1966, Michel Flynn has been proposed a simple model of categorizing all computers that still useful until now \cite{ref10}. His taxonomy considered the data and the operations performed on these data to produce four types of computer systems as follows:
+The main goal behind using parallel computer is to solve the bigger problem faster.
+A collection of processing elements must work together to perform the final solution of the main problem. However, many different architectures have been proposed
+and classified according to parallelism in instruction and data
+streams. In 1966, Michel Flynn has proposed a simple model to categorize all computers models that still useful until now \cite{ref10}. His taxonomy is based on considering the data and the operations performed on this data to produce four types of computer systems as follows:
\begin{itemize}
-\item \textbf{Single instruction, single data (SISD) stream}: A single processor executes a single instruction stream executing one data stream stored in an individual memory model, see figure \ref{fig:ch1:6}. As an example of this type is the conventional sequential computer system according to the Von Neumann model, it is also called the Uniprocessors.
+\item \textbf{Single instruction, single data (SISD) stream}: A single processor that executes a single instruction stream (i.e executing one data stream stored in an individual memory model, see figure \ref{fig:ch1:6}).
+The conventional sequential computer, according to Von Neumann model, also called the Uniprocessors can de viewed as an example of this type.
\begin{figure}[h!]
\centering
\includegraphics[scale=1]{fig/ch1/sisd.pdf}
\label{fig:ch1:6}
\end{figure}
-\item \textbf{Single instruction, multiple data (SIMD) stream}: All the processors execute the same instructions on different data.
-Each processor stores the data in its local memory, the processor communicates with each others typically via a simple communication model, see figure \ref{fig:ch1:7}. Many scientific and engineering
-applications are suitable to this type of parallel scheme.
+\item \textbf{Single instruction, multiple data (SIMD) stream}: All processors execute the same instructions on different data.
+Each processor stores the data in its local memory. Then, it communicates with each others typically via a simple communication model, see figure \ref{fig:ch1:7}. Many scientific and engineering
+applications are referred to this type of parallel scheme.
Vector and array processors are well known examples of this type.
-As an example about the applications executed over this architecture are graphics processing, video compression and medical image analysis applications.
+Examples about the applications executed over this architecture: (1) graphics processing, (2) video compression and (3) medical image analysis applications.
\begin{figure}[h!]
\centering
\label{fig:ch1:7}
\end{figure}
-\item \textbf{Multiple instruction, single data (MISD) stream}: Many operations from multiple processing elements are executed over the same data stream. Each processing element has its local memory to store the private program instructions applied to unique global memory data stream as in figure \ref{fig:ch1:8}. While the MISD machine is not commonly used, there are some interesting uses such as the systolic arrays and dataflow machines.
+\item \textbf{Multiple instruction, single data (MISD) stream}: Many operations from multiple processing elements are executed over the same data stream. Each processing element has its local memory to store the private program instructions. Then, these instructions are applied to unique global memory data stream as in figure \ref{fig:ch1:8}. While the MISD machine is not commonly used, there are some interesting uses such as the systolic arrays and dataflow machines.
\begin{figure}[h!]
\centering
\end{figure}
-\item \textbf{Multiple instruction, Multiple data (MIMD) stream}: There are multiple processing elements, each of which has a separate instruction and local data memories.
-At any time, different processing elements may be executing different instructions on the different data fragment, see figure \ref{fig:ch1:9}. There are two types of MIMD machines: the shared memory and the message passing MIMD machines.
-In the shared memory architectures, processors are communicated via a shared memory model, while in the message passing architecture each processor has its own local memory and all processors communicate via a communication network model. The multi-core processors, local
-clusters and grid systems are an examples for MIMD machine.
-Many applications have been conducted over this architecture
+\item \textbf{Multiple instruction, Multiple data (MIMD) stream}: There are multiple processing elements, each one has a separate instruction and local data memories.
+At any time, different processing elements may be used to execute different instructions on different data fragment, see figure \ref{fig:ch1:9}. There are two types of MIMD machines: the shared memory and the message passing MIMD machines.
+In the former, processors are communicated via a shared memory model, while in the latter, each processor has its own local memory and all processors communicate with each other via a communication network model. The multi-core processors, local clusters and grid systems are some examples for MIMD machine.
+Many applications have been provided based on this architecture
such as computer-aided design, computer-aided manufacturing, simulation, modeling, iterative applications and so on.
\begin{figure}[h!]
The work of this thesis is dedicated to MIMD machine's architecture. Therefore, we discuss in
this chapter some of the commonly used parallel architectures that belong to MIMD machines.
As explained before, MIMD architectures can be classified into two types, the shared memory and the distributed message passing ones. Furthermore, these classifications are based on
-how MIMD processors access the memory model. The shared MIMD machine communication topology can be bus-based, extended or hierarchical type. Whereas, the distributed memory MIMD machine may have hypercube or mesh interconnected networks. In the following are some well known MIMD parallel computing platforms:
+how MIMD processors access the memory model. The shared MIMD machine communication topology can be bus-based, extended or hierarchical type. Whereas, the distributed memory MIMD machine may have hypercube or mesh interconnected networks. In the following some well known MIMD parallel computing platforms are explained:
\begin{itemize}
\item \textbf{Multi-core processors}:
-The multi-core processor is a single chip component with two or more processing units.
-These processing units are called cores, which connected with each other via main memory model as in the figure \ref{fig:ch1:10}. Each individual core has its cache memory to store its data and execute different data or instruction stream in parallel. Moreover, each core can have one or more threads to execute a specific programming task as shown in the thread-level parallelism. Historically, the multi-cores of the CPU began as a two-core processors, with an increase in the number of cores approximately by double with each semiconductor process generation \cite{ref12}. The very quick improvements in the performance and thus the increase in the number of cores is devoted in the graphics processing unit (GPU). A current exemplar of the GPU is the NVIDIA GeForce TITAN Z with 5700 cores in the year of 2015 \cite{ref17}. While the general-purpose microprocessor (CPU) has less number of the cores, for example the TILE-MX processor from Tilera has 100 cores in the same year \cite{ref16}.
+The multi-core processor is a single chip component with two or more processing units. These processing units are called cores, which are connected to each other via a main memory model as in the figure \ref{fig:ch1:10}. Each individual core has its cache memory to store its data to execute different data or instruction streams in parallel. Moreover, each core may have one or more threads to execute a specific programming task as shown in the thread-level parallelism. Historically, the multi-cores of the CPU began as a two-core processors, with an increase in the number of cores approximately by double with each semiconductor process generation \cite{ref12}. The very quick improvements in the performance and the increase in the number of cores are devoted in the graphics processing unit (GPU). A current exemplar of the GPU is the NVIDIA GeForce TITAN Z with 5700 cores in the year of 2015 \cite{ref17}. While, in the same year the general-purpose microprocessor (CPU) has been appeared with less number of the cores, for example the TILE-MX processor from Tilera has 100 cores \cite{ref16}.
For more details about the multi-core processors see \cite{ref15}.
\begin{figure}[h!]
\item \textbf{Local Cluster}:
is a collection of independent computers that are connected
to each other via standard network switches and cables, which is a high speed
-local area network (LAN) with low latency and big bandwidth. Moreover, each node is distributed from each other and it communicates with other nodes using distributed message passing model. All the nodes in the cluster must be controlled by one node called the master node, which is a specific node uses to handle the scheduling and management of the other nodes as shown in the figure \ref{fig:ch1:11}. Usually, the hardware specifications of all nodes are homogeneous in term of the computing power and memory and thus it is called tightly-coupled fashion. Also, each computing node in the cluster has the same copy of the operating system. See \cite{ref18, ref19} for more information about the cluster and its applications.
+local area network (LAN) with low latency and big bandwidth. Moreover, each node is distributed from each other and communicates with other nodes using distributed message passing model. All the nodes in the cluster must be controlled by one node called the master node, which is a specific node used to handle the scheduling and the management of the other nodes as shown in the figure \ref{fig:ch1:11}. Usually, the hardware specifications of all nodes are homogeneous in term of computing power and memory. Thus, it is called tightly-coupled fashion. Also, each computing node in the cluster has the same copy of the operating system. See \cite{ref18, ref19} for more information about the cluster and its applications.
\begin{figure}[h!]
\centering
\item \textbf{Grid (Distributed clusters)}:
-Grid is a collection of local computing clusters from different sites connected via wide area network (WAN), which can be appeared virtually to the benefit users as a complete computing system \cite{ref20}.
-In particular, different local clusters composing the grid are geographically far away from each others. Usually, each local cluster composed of homogeneous nodes, which are different from the nodes of the others cluster located in different sites. These nodes can be different in the hardware and software specifications such as the computing power, memory size, operating system, local network latency and bandwidth. Figure \ref{fig:ch1:12} presents an example of the grid composed of three heterogeneous local clusters located in different sites which are connected throw a wide area network. Furthermore, the grid can be referred to an infrastructure applies the integration and the collaboration by using a collection of different computers, networks, database servers and scientific devices belong to many companies and universities. Therefore, wide heterogeneous computing resources are allowed to many users simultaneously. While the only bottleneck of the grid is the high latency communications between the nodes from different sites. The grid is also called the loosely-coupled fashion platform. However, the fault tolerance is required to guarantee the process of sending and receiving the messages between the computing nodes and thus keeps all the messages from loss.
+Grid is a collection of local computing clusters from different sites that are connected via a wide area network (WAN), which can be appeared virtually to the benefit of users to form a complete computing system \cite{ref20}.
+In particular, different local clusters compose the grid are geographically located far away from each others. Usually, each local cluster is composed of homogeneous nodes, which are different from nodes of the other clusters located in different sites. These nodes can be different in its hardware and software specifications (i.e its computing power, its memory size, its operating system and its local network latency and bandwidth. Figure \ref{fig:ch1:12} presents an example of a grid that is composed of three heterogeneous local clusters that are located in different sites and connected via a wide area network. Furthermore, the grid can be referred to an infrastructure that applies the integration and the collaboration by using a collection of different computers, networks, database servers and scientific devices, which are belong to many companies and universities. Therefore, wide heterogeneous computing resources are available to be used simultaneously by different user. Let's indicates that, the only bottleneck of the grid is the high latency communications between the nodes from different sites. The grid is also called the loosely-coupled fashion platform. However, the fault tolerance is required to guarantee the process of sending and receiving of messages between the computing nodes. Thus, it safely protects all messages against loss.
\begin{figure}[h!]
\centering
\end{itemize}
-Grid'5000 \cite{ref21} can be considered as a good example for this distributed platform.
+Grid'5000 \cite{ref21} can be considered as a good example of this distributed platform.
It is a large-scale testbed that consists of ten sites distributed
-all over metropolitan France and Luxembourg. These sites are: Grenoble, Lille, Luxembourg, Lyon, Nancy, Reims, Rennes , Sophia, Toulouse, Bordeaux. Figure \ref{fig:ch1:13} shows the geographical distribution of grid'5000 sites over France and Luxembourg. All the sites are connected together via a special long distance network called RENATER, which is the French
+all over metropolitan France and Luxembourg. These sites are: Grenoble, Lille, Luxembourg, Lyon, Nancy, Reims, Rennes , Sophia, Toulouse, Bordeaux. Figure \ref{fig:ch1:13} shows the geographical distribution of grid'5000 sites over France and Luxembourg. All the sites are connected together via a special long distance network called RENATER, which is abbreviation of the French
National Telecommunication Network for Technology. Each site in the grid is
composed of a few heterogeneous computing clusters and each cluster contains
many homogeneous nodes. In total, Grid'5000 has about one thousand heterogeneous nodes and eight thousand cores. In each site, the clusters and their nodes
are connected via high speed local area networks. Two types of local networks
are used, Ethernet or Infiniband networks, which have different characteristics
in terms of bandwidth and latency.
-Grid'5000 is dedicated as a test-bed for grid computing and thus users can book the required nodes from different sites. It allows the user to deploy his configured image of the operating system over the reserved nodes. Therefore, many software tools are available to the user to control and manage the reservation and deployment processes from his local machine. For example, OAR \cite{ref22} is a batch scheduler used to manage the heterogeneous resources of the grid'5000.
+Grid'5000 is dedicated as a test-bed for grid computing and thus users can book the required nodes from different sites.
+It also gives the opportunity to the users to deploy their configured image of the operating system over the reserved nodes.
+Indeed, many software tools are available for users in order to control and manage the reservation and deployment processes from their local machines. For example, OAR \cite{ref22} is a batch scheduler that is used to manage the heterogeneous resources of the grid'5000.
\subsection{Parallel programming Models}
\label{ch1:2:2}
-There are many parallel programming languages and libraries have been developed
+There are many parallel programming languages and libraries that have been developed
to explore the computing power of the parallel architectures. In this section,
-the parallel programming languages are divided into two main types,
-which is the shared and the distributed programming models. Moreover, each type is divided into two subcategories according to its support level for the number of computing units composing the parallel platform.
+two types of parallel programming languages are investigated: (1) shared and (2) distributed programming models. Moreover, each type is divided into two subcategories according to their supporting level for the number of computing units from which the parallel platform is composed.
Figure \ref{fig:ch1:14} presents this classification hierarchy of the parallel programming
-models. It also shows three parallel language examples for each subcategory.
+models. Three parallel language examples for each subcategory are shown.
\begin{figure}[h!]
Many programming interfaces and libraries have been developed to compile and run the
-parallel applications over the parallel architectures. In the following are
-some examples for each type of the parallel programming models:
+parallel applications over the parallel architectures. In the following,
+some examples for each type of the parallel programming models are discussed:
\begin{itemize}
\item \textbf{Local cluster programming models}
\begin{itemize}
- \item \textbf{MPI} \cite{ref23} is the Message Passing Interface and it considers a
+ \item \textbf{MPI} \cite{ref23} is the Message Passing Interface and it id considered as a
standardization
- dedicated for message passing in a distributed memory environment.
- The first version of MPI designated by a group of researchers in
- 1991. It is a library, not a language and its subroutines
+ dedicated to message passing in a distributed memory environment.
+ The first version of MPI was designed by a group of researchers in
+ 1991. It consist of a library, not a language and its subroutines
can be called from many programming languages such as C, Fortran and
- Java. The programmes that users write in these languages are
- compiled with ordinary compilers and linked with the MPI library.
- Its library functions are not only for peer to peer operations throw
- send and receive messages, but it allowed many others collective
- operations such as gathering and reduction operations. MPI user, feel
+ Java. Programmes that write in these languages and
+ compile their codes with ordinary compilers are directly linked to MPI library.
+ library functions are not only limited to peer to peer operations for
+ sending and receiving messages, also it is related to many others collective
+ operations such as gathering and reduction operations. MPI user, feels
free from the network topology, synchronization and communication
functionality between a group of processes. Furthermore, it has an
asynchronous point to point operations, which make the computations
- to overlap with communications. While MPI is not devoted to a grid,
+ to overlap with communications. While MPI is not devoted to grid,
\textbf{MPICH} is one of the most
- popular implementations of MPI dedicated for grid computing. It uses
- as an extended version of MPI, which implements a fault tolerance
- \cite{ref52}. In this work, both of MPI and MPICH programming libraries
- have used for programming our algorithms and applications which called
- inside both of Fortran and C programming languages.
+ popular implementations of MPI dedicated for grid computing. It has been used
+ as an extended version of MPI, which has been implemented for fault tolerance
+ \cite{ref52}. In this work, both MPI and MPICH programming libraries
+ are used in programming of our algorithms and applications which are included
+ inside both Fortran and C programming languages.
- \item \textbf{PVM} \cite{ref25} is for Parallel Virtual Machine, which is a collection
- of software tools and libraries to allow users working over a
- heterogeneous set of machines to operate as a single high performance
- parallel platform. It is dedicated to a group of machine that are
- distributed and heterogeneous in the operating system environments.
+ \item \textbf{PVM} \cite{ref25} is included Parallel Virtual Machine, composed of a collection
+ of software tools and libraries that allow users to work over a
+ heterogeneous set of machines to perform a single high performance
+ parallel platform. It is dedicated to a group of machines that are
+ distributed heterogeneously the operating system environments.
The PVM system is elementary for parallel programming to be used with
- C, C++, and Fortran languages.
- It is considered more robust in fault tolerance than MPI, easier to
- add or delete the crashed nodes in the host pool
- \cite{ref26}. While MPI has, the more communication messages support and asynchronous
+ C, C++, and Fortran languages.
+ It supports more robustness in term of fault tolerance tan MPI.
+ Also, it is not complicated in term of adding or deleting the crashed
+ nodes in the host pool \cite{ref26}.
+ On the other side, MPI supports more more communication messages and asynchronous
operations which are not allowed in PVM.
+
\item \textbf{BLACS} \cite{ref27} is for Basic Linear Algebra Communication Subprograms.
- It has a collection of libraries that used to build a linear algebra message
- communication model which is applied effectively over distributed memory architectures.
- The primary goal of using BLACS is mapping a liner set or processors or any distributed
- machines into two dimensional array or grid, which offers an easy tool for building a
- linear algebra applications.
+ It consist of a collection of libraries that are used to build a linear algebra message
+ communication model. Thus, it is effectively applied over distributed memory architectures.
+ The primary goal of using BLACS is mapping a linear set or processors or any distributed
+ machines into two dimensional arrays or grid. Indeed, it offers an easy tool to build the
+ linear algebra based applications.
\end{itemize}
\item \textbf{Grid programming models}
\begin{itemize}
- \item \textbf{Gridsolve} \cite{ref28} is the first middleware for a grid and the
- high performance computing that offers a good tool to solve a complex
- scientific applications using distinct distributed machines. It applies the
- fault tolerance and load balancing features to ensure the reliability of the
+ \item \textbf{Gridsolve} \cite{ref28} is the first middleware for grid and the
+ high performance computing. It supports a good tool to solve complex
+ scientific applications using distinct distributed machines. Also, it satisfies the
+ fault tolerance and achieves the load balancing features to ensure the reliability of the
applications when running over a geographically distributed resources.
- It works with different programming languages such as C, C++, Java and Fortran.
+ It can be integrated with different programming languages such as C, C++, Java and Fortran.
- \item \textbf{GLOBAS} \cite{ref29,ref30} is the most widely standardization tool kit
- for a grid computing. It permits the users to share their computing resources securely.
- While the GLOBAS toolkit is allowed to work with a grid, it offers a fault
- detection mechanism to ensure the delivery of the messages.
- The first version of Globus toolkit appeared
- in 1998 and now the sixth version is available \cite{ref31}.
+ \item \textbf{GLOBAS} \cite{ref29,ref30} is the most widely standardization toolkit
+ for grid computing. It permits the users to share their computing resources securely.
+ Since, the GLOBAS toolkit has the opportunity to work with grid, then it offers a fault
+ detection mechanism to ensure the delivery of messages.
+ The first version of Globus toolkit has been appeared
+ in 1998. Recently, the sixth version of this toolkit is available now \cite{ref31}.
- \item \textbf{Legion} \cite{ref32,ref33} is an object-based and meta-systems software project
- at the University of Virginia on November 1997.
- It implements many features such as security, portability and fault tolerance.
- Moreover, it is created to support a wide degree of parallelism throw an easy
- programming tool to build the parallel applications.
+ \item \textbf{Legion} \cite{ref32,ref33} is an object-based, meta-systems software project,
+ invented by the University of Virginia on November 1997.
+ It ensures many features such as security, portability and fault tolerance.
+ Moreover, it has been created to support a wide degree of parallelism under the use of
+ an easy programming tool to build parallel applications.
\end{itemize}
\item \textbf{Multi-core CPU programming models}
\begin{itemize}
- \item \textbf{OpenMP} \cite{ref34} is a parallel programming tool for shared memory
+ \item \textbf{OpenMP} \cite{ref34} is a parallel programming tool dedicated to shared memory
architectures. The main goal of using this programming model is to provide
- a standard and portable API (application programming interface) for writing
- shared memory parallel programs. It can be used with programming languages such
- as C, C++ and Fortran to support different types of shared memory platforms
+ a standard and portable API (application programming interface) to write
+ shared memory parallel programs. It can be used with many programming languages such
+ as C, C++ and Fortran in order to support different types of shared memory platforms
such as multi-core processors.
OpenMP uses multi-threading, which is a method of parallel programming
that uses a master thread to control a set of slave threads. Each
- thread can be executed in a parallel by allocating it to a processor.
- Moreover, OpenMP can be used with MPI to support hybrid platforms that have
+ thread can be executed in parallel by allocating it to one processor.
+ Moreover, OpenMP can be used with MPI to support hybrid platforms which have
shared and distributed memory models at the same time.
\item \textbf{Cilk} \cite{ref13,ref35} is a linguistic and runtime technology for algorithmic
- multi-threaded programming originally developed at MIT.
+ multi-threaded programming originally developed by MIT.
It allows the programmer to focus on building the program in a structured way
- to discover the inherent parallelism. Many specifications are used in Cilk
- such as the load balancing, synchronization and communication protocols.
+ in order to discover the inherent parallelism. Many specifications are used in Cilk
+ such as load balancing, synchronization and communication protocols.
- \item \textbf{TBB} \cite{ref36} is for Threading Building Blocks, is a software library used with
- C++ programming language for multi-core parallel programming developed by Intel.
- It works on the principle of dividing the computations into many tasks that can be
- executed in a parallel.
- It also has a management library to schedule the parallel task execution.
- The difference between OpenMP and TBB, is the latter uses a task-based scheduling
- mechanism. Furthermore, TBB is more popular with C++ programming language than
- other languages. It is designed to work with any compiler environments, and thus
- it is easily ported to a new platform. Hence, TBB has been ported to
- different types of operating systems and processors. It has limited
- support to vector processing architecture and then it is connected with OpenMP
- and Cilk to support this platform.
+ \item \textbf{TBB} \cite{ref36} Abbreviation of Threading Building Blocks. It is a software library
+ used with
+ C++ programming language for multi-core parallel programming that has been developed by Intel.
+ It works on the principle of dividing the computations into many tasks and
+ executing them in parallel.
+ Also, It has a management library to schedule the parallel task execution.
+ The only difference between OpenMP and TBB, is that TBB uses a task-based scheduling
+ mechanism. For that reason, TBB is more popular with C++ programming language than
+ other languages. Additionally, it has the ability to work with any compiler environments.
+ Hence, it can be easily supported by any new platform. Therefore, TBB has been supported by
+ different types of operating systems and processors.
+ Noting that, it is still has some limitations to support vector processing architecture.
+ For this reason, it is connected with with OpenMP and Cilk to overcome this limitations.
+
\end{itemize}
\item \textbf{GPU programming models}
\begin{itemize}
\item \textbf{CUDA} \cite{ref37} Modern graphical processing units (GPUs) have increased its chip-level
- parallelism. Current NVIDIA GPUs are many-cores processor having thousands
- of cores. According to this massively core parallelism, the NVIDIA in 2007 developed
- a parallel programming language called CUDA , which is for Compute Unified Device
- Architecture. A CUDA program has two parts, the first one is called a host which is a
- set of threads that executed sequentially over the CPU. The second part is called the
- kernels, which are a set of threads that can be executed in a parallel over the GPUs.
+ parallelism. Current NVIDIA GPUs consisted of many-cores processor that have
+ thousands of cores. According to this massively core parallelism, in 2007 the NVIDIA
+ has developed CUDA as parallel programming language, which is Compute Unified Device
+ Architecture. A CUDA program has two parts: hosts and kernels. The host is a
+ set of threads that are sequentially executed over the CPU.
+ While, the kernel is a set of threads that can be executed in parallel over the GPUs.
\item \textbf{OpenCL}\cite{ref38} is for Open Computing Language. It is a parallel
programming language dedicated for heterogeneous platform composed
- of CPUs and GPUs. The first release initially developed by Apple
- in 2008. Functions executed on an OpenCL device are called kernels,
+ of CPUs and GPUs. The first release of this language has initially developed by Apple
+ in 2008. Functions that are executed over OpenCL devices are called kernels,
which can be portable execute on any computing hardware such as CPU or GPU cores.
This parallel programming language supports the homogeneous shared memory
platforms and the multi-core processors by using one core for control
and the others for computing.
- \item \textbf{HLSL} \cite{ref39} is for High Level Shading Language, is the shader
+ \item \textbf{HLSL} \cite{ref39} is named as the High Level Shading Language and defined as the shader
programming language for Direct3D, which is a part of
Microsoft’s DirectX API. It supports the shader design with
C language syntax, types, expressions, statements, and functions and it
provides a graphical pipeline parallelism.
- The last version of HLSL is version 5.0 of DirectX 11, which adds a new
+ The last version of HLSL is the version 5.0 of DirectX 11, which has added a new
general-purpose GPU functions like CUDA. Recently, the new OpenCL
version has started to replace CUDA as a multi-platform GPU language.
\section{Iterative Methods}
\label{ch1:3}
-Numerical methods are a scientific computation for solving linear and non-linear problems.
-Almost of the numerical problems can be represented by a mathematical equation form with relations between its components. For example, solving linear equations which are well known in the scientific area is generally expressed in the following form:
+Numerical methods are defined as a scientific computation methods to solve linear and non-linear problems.
+Most of the numerical problems can be represented by a mathematical equation form with relations between its components. For example, solving linear equations which are well known in the scientific area is generally expressed in the following form:
\begin{equation}
\label{eq:linear}
\end{equation}
Where $A$ is a two dimensional matrix of size $N \times N$, $x$ is the unknown vector,
-and $b$ is a vector of constant, each of size $N$. There are two types of solution methods for solving this linear system.
-The first method is called \textbf{Direct methods}, which is a finite number of steps depending on the
-size of the linear system to give the exact solution. If the problem size is very big these methods are expensive or their
-solutions are impossible in some cases. The second type is called \textbf{Iterative methods}, which is computed
-many times the same block of the operations starting from the initial vector until reaching to the acceptable
+and $b$ is a vector of constant, each of size $N$. There are two types of solution methods to solve this linear system.
+The first method is called \textbf{Direct methods}, which consist of a finite number of steps depending on the
+size of the linear system to give the exact solution. If the problem size is very big, these methods are expensive or their
+solutions are impossible in some cases. The second type is called \textbf{Iterative methods}, which computes
+the same block of operations several times, starting from the initial vector until reaching the acceptable
approximation of the exact solution. However, the iterative methods are faster than direct methods and can be
-applied in parallel. Moreover, iterative methods can be used to solve both of the linear and non-linear equations.
-In our work, we are interested in parallelizing the iterative methods because they are more popular and effective than direct ones.
+effectively applied in parallel. Moreover, iterative methods can be used to solve both linear and non-linear equations.
+In our work, we are interested to paralleize the iterative methods because they are more popular and more efficient than direct ones.
The sequential iterative algorithm is typically organized as a series of steps essentially of the form:
X^{(k+1)} \longleftarrow F(X^k)
\end{equation}
-Where $F$ is one or set of operations applied to the data vector $X^k$ to produce the new data vector $X^{(k+1)}$. This operation $F$ is applied sequentially many times until convergence condition is satisfy as in the algorithm \ref{sia}.
+Where $F$ is one or set of operations applied to the data vector $X^k$ to produce the new data vector $X^{(k+1)}$. The operation $F$ is applied sequentially many times until satisfying the convergence condition as in the algorithm \ref{sia}.
\end{algorithm}
-The sequential iterative algorithm at each iteration computes the value of the relative error, which is called the residual that denoted as $R$. This error value is the maximum difference between the data components of the vectors of the last two successive iterations as follows:
+The sequential iterative algorithm at each iteration computes the value of the relative error, which is called the residual and denoted as $R$. This error value is the maximum difference between the data components of the vectors of the last two successive iterations as follows:
\begin{equation}
\label{eq:res}
R = \max_{i=1, \dots, N} \abs{X_i^{(k+1)} - X_i^k}
\end{equation}
-Where $N$ is the size of the vector $X$. Then, the iterative sequential algorithm stops its iterations if the maximum error between the last two successive solution vectors, as in \ref{eq:res}, is less than or equal to the some threshold value. Otherwise, it replaces the new vector $X^{(k+1)}$ with the old vector $X^k$ and computes the new iteration.
+Where $N$ is the size of the vector $X$. Then, the iterative sequential algorithm stops its iterations if the maximum error between the last two successive solution vectors, as in \ref{eq:res}, is less than or equal to some threshold values. Otherwise, it replaces the new vector $X^{(k+1)}$ with the old vector $X^k$ and computes the new iteration.
\subsection{Synchronous Parallel Iterative method}
\label{ch1:3:1}
In the synchronous iterative algorithm, computing processors need to communicate with each others to
-exchange data at each iteration. Algorithm \ref{spia} can be used synchronous iterations and synchronous communications and denoted as \textbf{SISC} model. At each iteration, the computing processor waits until
-it has received all the data computed at the previous iteration from the other processors to perform the next iteration. This type of communication model uses if there is a dependency between the parallel tasks. Figure \ref{fig:ch1:15}, shows that using SICS model in a heterogeneous platform may result in a big period of the idle times represented by the white dashed spaces between two successive iterations. Indeed, this happens when the fast computing processor waits for the slow ones to finish their iterations to be able to synchronously send its data to them. This operation wastes a big amount of the computing power of the faster processors and thus their energy consumptions. The increase in the level of the heterogeneity between the computing powers of the computing processors may increase propositionally these idle times.
-Accordingly, this algorithm is effectively implemented over a local cluster where a high speed local network is used to reduce these idle times.
+exchange data at each iteration. Algorithm \ref{spia} can used synchronous iterations and synchronous communications denoted as \textbf{SISC} model. At each iteration, the computing processor waits until
+it receives all the computed data at the previous iteration from other processors to perform the next iteration. This type of communication model uses if there is a dependency between the parallel tasks. Figure \ref{fig:ch1:15}, shows that using SICS model in a heterogeneous platform may result in a big period of the idle times represented by the white dashed spaces between two successive iterations. Indeed, this happens when the faster computing processor waits for the slower ones to finish their iterations to be able to synchronously send its data to them.
+Using this operation, faster processors wast a big amount of their computing power and thus their energy consumption.
+The increase in the heterogeneity level between computing powers of the computing processors may increase propositionally these idle times.
+Accordingly, this algorithm is effectively implemented over a local cluster, where a high speed local network is used to reduce these idle times.
\begin{figure}[h!]
\label{fig:ch1:16}
\end{figure}
-Furthermore, the communications of the synchronous iterative algorithm can be implemented asynchronously. Therefore, this algorithm is called the synchronous iteration and asynchronous
-communication algorithm and denoted as \textbf{SIAC} algorithm. The main principle of this algorithm is to use a synchronized iterations while exchanging the data between the computing units asynchronously.
-Moreover, each computing unit doesn't have to wait for its neighbours to receive the data messages
-that its has sent, while it only waits for receiving the data from them. This can be implemented with SISC algorithm programmed in MPI by replacing the synchronous send of the messages by asynchronous ones and keeps
-the synchronous receive of the data messages. The only advantage of this technique is to reduce the idle times between the iterations by making the communications to overlap partially
+Furthermore, the communications of the synchronous iterative algorithm can be implemented asynchronously. Therefore, this algorithm is called Synchronous Iteration and Asynchronous
+Communication and denoted as \textbf{SIAC} algorithm. The main principle of this algorithm is to use a synchronized iterations while exchanging the data between the computing units asynchronously.
+Moreover, each computing unit doesn't need to wait for its neighbours to receive the data messages
+that it has sent, while it only waits to receive data from them. This can be implemented with SISC algorithm that is programmed in MPI by replacing the synchronous send of the messages by asynchronous ones, while keeping
+the synchronous receive. The only advantage of this technique is to reduce the idle times between iterations by allowing the communications to overlap partially
with computations, see figure \ref{fig:ch1:16}. The idle times are not totally eliminated because the
-fast computing nodes still have to wait for slow ones to send their data messages.
-Both of the SISC and SIAC algorithms are not tolerated to the loss of data messages. Consequently, if one node is crashed, all the other computing nodes are blocked together and all the system is crashing.
+fast computing nodes must wait for slow ones to send their data messages.
+SISC and SIAC algorithms are not tolerated to the loss of data messages. Consequently, if one node is crashed, all the other computing nodes are blocked together and all the system is crashed.
\subsection{Asynchronous Parallel Iterative method}
\label{ch1:3:2}
-The asynchronous iterations mean that all processors perform their iterations without considering the works of the other processors. Each processor doesn't have to wait for receiving
-the data messages from the other processors and continue computing the next iteration depending on its own data received at a specific time. While all processors don't have to wait
-for data delivery from each other, there are not existence of the idle times at all between the iterations as in figure \ref{fig:ch1:17}. This figure indicates that the fast processors can perform more iterations than the others at the same time.
-Hence, the asynchronous iterative algorithm uses an asynchronous communications is called \textbf{AIAC} algorithm. Likewise the SISC algorithm, the AIAC algorithm subdivides the global Vectors $X$ into $M$ sub-vectors between the computing units. The main difference between the two algorithms is that these $M$ sub-vectors are not updated at each iteration in the AIAC algorithm because both of the iterations and communications are asynchronous.
-However, there are two mechanisms to update the data vectors in AIAC algorithm as follows:
+The asynchronous iterations mean that all processors perform their iterations without considering the works of other processors. Each processor doesn't have to wait to receive
+data messages from other processors and continues to compute the next iteration depending on its own data received at a specific time. While all processors don't have to wait
+for data delivery from each other, there are not existence of the idle times at all between the iterations as in figure \ref{fig:ch1:17}. This figure indicates that fast processors can perform more iterations than others at the same time.
+Hence, the asynchronous iterative algorithm that uses an asynchronous communications is called \textbf{AIAC} algorithm. Similarly to the SISC algorithm, the AIAC algorithm subdivides the global vectors $X$ into $M$ sub-vectors between the computing units. The main difference between the two algorithms is that these $M$ sub-vectors are not updated at each iteration in the AIAC algorithm because both iterations and communications are asynchronous.
+However, there are two mechanisms to update data vectors in AIAC algorithm which are:
\begin{itemize}
\item The local vectors can be updated randomly on the order of $M$ computing units.
- This leads to some of these local vectors to not update at a certain time.
- \item According to the time period $t$, each computing unit checks if one of the its
- dependencies components have been updated. If the computing node detects any update
- case, it updates its own local vector data using the last received data messages.
- Otherwise, it does nothing at the time $t$.
+ Indeed, some of these local vectors may be not able to update at a certain time.
+ \item According to the time period $t$, each computing unit checks if one of its
+ dependencies components has been updated. If the computing node detects any update,
+ then it updates its own local vector data using the last received data messages.
+ Otherwise, nothing is occurred at the time $t$.
\end{itemize}
\end{figure}
The global convergence of the parallel iterative method depends on the scientific application.
-For more information about the convergence detection techniques of the asynchronous iterative methods,
-we refer to \cite{ref40,ref41,ref42,ref43} for more details.
+For more information about the convergence detection techniques of the asynchronous iterative methods, refer to \cite{ref40,ref41,ref42,ref43} for more details.
-The implementation of the AIAC method is not easy, but it gives many advantages over the traditional synchronous iterative method:
+The implementation of the AIAC method is not easy, but it gives many advantages over the traditional synchronous iterative method. These features can be summarized as follows:
\begin{itemize}
-\item It prevents the existence of the idle times because each processor doesn't have to wait
- for the others to receive the data messages. Then, there are no idle times between each two
+\item It prevents the existence of the idle times, since each processor doesn't have to wait
+ for others to receive the data messages. Then, there are no idle times between each two
successive iterations.
\item Less sensitive for the heterogeneous communications and nodes' computing powers. In heterogeneous
- platform, the faster nodes don't have to wait for the slow ones and so it performs more iterations than
- them. While in the traditional synchronous iterative methods, the fast computing nodes perform the same
+ platform, the faster nodes don't need to wait for the slow ones, so it can perform more iterations compared
+ to them. While in the traditional synchronous iterative methods, the fast computing nodes perform the same
number of iterations as the slow ones because they are blocked together.
-\item The loss of the data messages is totally tolerant because each computing unit is not
- blocked by the others. If the message is lost, the destination node doesn't have to wait
+\item The loss of the data messages is totally tolerant because each computing unit can not to be
+ blocked by others. If the message is lost, the destination node doesn't have to wait
for this data message and it uses the last received data to perform its iteration
independently.
\item In the distributed grid architecture, the local clusters from different sites are
connected via slow network with a high latency. On the other hand, the use of the AIAC model
reduces the delay of sending the data message over such slow network link and thus the performance
- of the applications is improved.
+ of applications is improved.
\end{itemize}
In addition to the difficulty of applying the asynchronous iterative method, it has some
-disadvantages as follows:
+disadvantages that can be summarized by these points:
\begin{itemize}
\item It is not compatible with all types of the iterative applications because some of these
- applications need to receive the data messages from its neighbours at each iteration.
+ applications need to receive data messages from its neighbours at each iteration.
Therefore, they required a fix number of iterations to converge. Otherwise, the
- application performs an infinity number of iterations and then all of the system
- is crashing.
+ application performs an infinity number of iterations which provides a system crash.
\item The application of an asynchronous iterative method requires more iterations compared
to the synchronous ones to converge when it is executed over the local cluster.
- The increase in the number of the iterations may increase proportionally
+ The increase in the number of iterations may increase proportionally
the execution time of the application.
Especially, the local computing cluster uses a high speed network, then running the
synchronous version over such platform is quicker to converge.
synchronous iterative methods for detecting the global convergence cannot be used for
asynchronous ones. Therefore, in AIAC algorithm a process can perform many iterations
without receiving any data messages from its neighbours. The absence of receiving new
- data messages makes the data component not vary at the computing units and thus it detect
+ data messages makes the data component invariant at the computing units and thus it provides
a false local convergence. This means that the local residual value is less than the
required threshold. This fake convergence is conflicted at the reception of the first data message
because the local subsystem will locally diverge after computing the next iteration.
Generally, the interested readers can find more details about both of synchronous and asynchronous
iterative methods in \cite{ref44,ref45}.
-In our works, we are interested to implement both of a synchronous and asynchronous
-iterative methods for solving different problems over local homogeneous cluster, local heterogeneous cluster and distributed grid. Accordingly, the process of optimizing their energy consumptions and performance is the main objective of this work as shown in the next chapters.
+In our works, we are interested to implement both synchronous and asynchronous
+iterative methods to solve different problems over local homogeneous cluster, local heterogeneous cluster and distributed grid. Accordingly, the process of optimizing their energy consumptions and their performance is the main objective of this work as will be discussed in the next chapters.
\section{The energy consumption model of the parallel applications }
\label{ch1:4}
Many researchers~\cite{ref46,ref47,ref48,ref49} divide the power consumed by a processor into
-two power metrics: the static and the dynamic power. The first one is
+two power metrics: static power and dynamic power. The first one is
consumed as long as the computing unit is on, the latter is only consumed during
computation times. The dynamic power $P_{dyn}$ is related to the switching
activity $\alpha$, load capacitance $C_L$, the supply voltage $V$ and
\end{equation}
-According to \cite{ref46,ref47}, the static power consumption $P_{static}$ is not changes when the frequency of the processors is scaled down. Therefore, the static energy consumption can be computed as follows:
+According to \cite{ref46,ref47}, the static power consumption $P_{static}$ does not changed when the frequency of the processors is scaled down. Therefore, the static energy consumption can be computed as follows:
\begin{equation}
\label{eq:Estatic}
E_{static} = S \cdot P_{static} \cdot T
Depending on \ref{eq:Eind}, the total energy consumption of $N$ parallel task running on $N$ processors is the summation of the individual energies consumed by all processors. This model is developed and used by Rauber and Rünger~\cite{ref47}. They modeled
-the total energy consumption for a parallel tasks running on a homogeneous platform by sorting the execution time of the all parallel tasks in a descending order, then their model can be written as a function of the scaling factor $S$, as in EQ~(\ref{eq:energy}).
+the total energy consumption for parallel tasks running on a homogeneous platform by sorting the execution time of the all parallel tasks in a descending order, then their model can be written as a function of the scaling factor $S$, as in EQ~(\ref{eq:energy}).
\begin{equation}
\label{eq:energy}
\item It is not well adapted to a heterogeneous architectures when there are different
types of the processors, which are consumed different dynamic and static powers. Then, this model is
not able to measure the energy consumption of all the parallel systems because it depends on
- one value for each of the static and dynamic powers.
+ one value for the static and dynamic powers.
\end{itemize}
-Therefore, one of the more important goals of this work is to develop energy models that
-has be taken into consideration the communication times in addition to computation times to modelize and measure the energy consumptions of the parallel iterative methods. These models are dedicated to all parallel architectures such as the homogeneous and heterogeneous platforms, which may be local or distributed computing clusters.
+Therefore, one of the more important goals of this work is to develop a new energy models that
+must be taken into consideration the communication times in addition to the computation times in order to modelize and measure the energy consumptions of the parallel iterative methods. These models must be suitable to efficiently integrate with all parallel architectures such as the homogeneous and heterogeneous platforms, with its local or distributed computing clusters.
\section{Conclusion}
\label{ch1:5}
-In this chapter, three sections have been presented for describing the parallel hardware architectures, parallel iterative applications and the energy consumption model used to measure the energies of these applications.
-In the first section, different types of parallelism levels that can be implemented in a software and hardware techniques have explained. Furthermore, the types of the parallel architectures are demonstrated and classified according to how their computing units are connected to a memory model.
-Both of the shared and distributed platforms are demonstrated and depending on them the parallel programming models have categorized.
-In the second section, the two types of parallel iterative methods are described as synchronous and asynchronous iterative methods. The synchronous iterative methods are well implemented over local homogeneous cluster with a high speed network link, while the asynchronous iterative methods are more conventional to implement over the distributed heterogeneous clusters.
-Finally, in the third section, an energy consumption model used for measuring the energy consumption of the parallel applications from the related literature has described. This model cannot be used for all types of parallel architectures. Indeed, it assumes measuring the dynamic power during both of the communication and computation times, while the processor involved remains idle during the communication times and only consumes the static power. Moreover, it is not well adapted to heterogeneous architectures when there are different types of the processors, which are consumed different dynamic and static powers at the same time.
-
-However, in the next chapters of this thesis a new energy consumption models are developed, and how these
-energy models are used for modeling and measuring the energy consumptions by parallel iterative methods running on both homogeneous and heterogeneous architectures. Furthermore, these energy models use in a method for optimizing both of the energy consumption and the performance of the iterative message passing applications.
\ No newline at end of file
+In this chapter, three sections have been presented to describe the parallel hardware architectures, parallel iterative applications and the energy consumption model used to measure the energies of these applications.
+The different types of parallelism levels that can be implemented in software and hardware techniques have been explained in the first section. Furthermore, different types of parallel architectures have been discussed and classified according to the connection between the computation units and the memory model.
+Both shared and distributed platforms as well as its depending parallel programming models have been categorized.
+In the second section, the two types of parallel iterative methods: synchronous and asynchronous ones are investigated.
+The synchronous iterative methods are well implemented over local homogeneous cluster with a high speed network link, while the asynchronous iterative methods are more conventional to implement over the distributed heterogeneous clusters.
+Finally, in the third section, an energy consumption model proposed in the state of the art to measure the energy consumption of parallel applications is explained. This model cannot be used for all types of parallel architectures. Since, it assumes to measure the dynamic power during both of the communication and computation times, while the processor involved remains idle during the communication times and only consumes the static power. Moreover, it is not well adapted to heterogeneous architectures when there are different types of the processors, that consume different dynamic and static powers at the same time.
+
+For these reasons, in the next chapters of this thesis a new energy consumption models are developed to effectively integrate in modeling and measuring the energy consumptions by parallel iterative methods running on both homogeneous and heterogeneous architectures. Additionally, these energy models are used in a method to optimize both energy consumption and performance of the iterative message passing applications.
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