X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/ThesisAhmed.git/blobdiff_plain/66a6ac6fefa290df8ced335eb61525e7209e6b89..6afb8b5a72182ed5bc67626bad7073bb45150c1c:/CHAPITRE_01.tex?ds=sidebyside

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@@ -771,7 +771,7 @@ has be taken into consideration the communication times in addition to computati
 In this chapter, three sections have been presented for describing the parallel hardware architectures, parallel iterative applications and the energy consumption model used to measure the energies of these applications. 
 In the first section, different types of parallelism levels that can be implemented in a software and hardware techniques have explained. Furthermore, the types of the parallel architectures are demonstrated and classified according to how the computing units are connected to a memory model.  
 Both of the shared and distributed platforms are demonstrated and depending on them the parallel programming models have categorized. 
-In the second section, the two types parallel iterative methods are described as synchronous and asynchronous iterative methods. The synchronous iterative methods are well implemented over local homogeneous cluster with a high speed network link, while the asynchronous iterative methods are more conventional to implement over the distributed heterogeneous clusters. 
+In the second section, the two types of parallel iterative methods are described as synchronous and asynchronous iterative methods. The synchronous iterative methods are well implemented over local homogeneous cluster with a high speed network link, while the asynchronous iterative methods are more conventional to implement over the distributed heterogeneous clusters. 
 Finally in the third section, the energy consumption model used for measuring the energy consumption of the parallel applications from the related literature is  described. This model  cannot be used for all types of parallel architectures. Indeed, it assumes  measuring the dynamic power during both of the communication and computation times, while the processor involved remains idle during the communication times and  only consumes the static power. Moreover, it is not well adapted to  heterogeneous architectures when there are different types of the processors, which are consumed different dynamic and static powers at the same time.
 
 However, in the next chapters of this thesis a new energy consumption models are developed, and how these
