1 <!DOCTYPE deserializer_3x1>
2 <block_impl ref_name="deserializer_3x1.xml" ref_md5="">
4 <author lastname="" mail="" firstname=""/>
5 <date creation="2018-01-10"/>
6 <related_files list=""/>
7 <description>gre</description>
12 <package name="std_logic_1164" use="all"/>
13 <package name="numeric_std" use="all"/>
18 signal do_out : std_logic;
19 signal data1_reg : std_logic_vector(in_width-1 downto 0);
20 signal data2_reg : std_logic_vector(in_width-1 downto 0);
22 signal count : unsigned(1 downto 0);
26 deser_process : process (@{clk}, @{reset})
28 if @{reset} = '1' then
29 count <= to_unsigned(0, 2);
30 data1_reg <= (others => '0');
31 data2_reg <= (others => '0');
32 @{data1_out} <= (others => '0');
33 @{data2_out} <= (others => '0');
34 @{data3_out} <= (others => '0');
37 elsif rising_edge(@{clk}) then
40 @{data1_out} <= (others => '0');
41 @{data2_out} <= (others => '0');
42 @{data3_out} <= (others => '0');
44 if @{data_in_enb} = '1' then
47 data1_reg <= @{data_in};
48 count <= count + 1;
50 data2_reg <= @{data_in};
51 count <= count + 1;
53 @{data1_out} <= data1_reg;
54 @{data2_out} <= data2_reg;
55 @{data3_out} <= @{data_in};
57 count <= to_unsigned(0, 2);
62 end process deser_process;
64 @{data1_out_enb} <= do_out;
65 @{data2_out_enb} <= do_out;
66 @{data3_out_enb} <= do_out;
71 <input pattern="111" name="data_in_enb"/>
73 <production counter="3">
74 <output pattern="0001" name="data1_out_enb"/>
75 <output pattern="0001" name="data2_out_enb"/>
76 <output pattern="0001" name="data3_out_enb"/>