lib/implementations/threshold_extctl_impl.xml

   1 <!DOCTYPE threshold_extctl>
   2 <block_impl ref_name="threshold_extctl.xml" ref_md5="">
   3   <comments>
   4     <author lastname="" mail="" firstname=""/>
   5     <date creation="2018-01-10"/>
   6     <related_files list=""/>
   7     <description>fez</description>
   8     <notes>fez</notes>
   9   </comments>
  10   <libraries>
  11     <library name="ieee">
  12       <package name="std_logic_1164" use="all"/>
  13       <package name="numeric_std" use="all"/>
  14     </library>
  15   </libraries>
  16   <architecture>
  17 -- Signals
  18 signal def_val : unsigned(in_width-1 downto 0);
  19
  20 begin
  21
  22 def_val &lt;= to_unsigned(default_value, in_width);
  23
  24 threshold_process : process (@{clk}, @{reset})
  25 begin
  26 if @{reset} = '1' then
  27
  28 @{data_out_enb} &lt;= '0';
  29 @{data_out} &lt;= (others => '0');
  30
  31 elsif rising_edge(@{clk}) then
  32
  33 @{data_out_enb} &lt;= '0';
  34
  35 if @{data_in_enb} = '1' and @{keep_in_enb} = '1' then
  36
  37 if @{keep_in} = '1' then
  38 @{data_out} &lt;= @{data_in};
  39 else
  40 @{data_out} &lt;= std_logic_vector(def_val);
  41 end if;
  42 @{data_out_enb} &lt;= '1';
  43 end if;
  44 end if;
  45 end process threshold_process;
  46
  47 end rtl;
  48 </architecture>
  49   <patterns>
  50     <delta value="1"/>
  51     <consumption>
  52       <input pattern="1" name="data_in_enb"/>
  53       <input pattern="1" name="keep_in_enb"/>
  54     </consumption>
  55     <production counter="1">
  56       <output pattern="01" name="data_out_enb"/>
  57     </production>
  58   </patterns>
  59 </block_impl>