-------------------------------------------------------------------------------
--
--  File          : threshold _extctl.vhd
--  Related files : 
--
--  Author(s)     : stephane Domas (sdomas@univ-fcomte.fr)
--
--  Creation Date : 2017/10/16
--
--  Description   : This IP does a threshold based on a external signal
--  
--
--  Note          : input data is kept as is depending on the fact that
--                  the keep_in signal is asserted to 1 or not. It it is not,
--                  then input is replaced by the default_value given as a
--                  generic. Note that keep_in_enb and data_in_enb must be
--                  asserted to 1 at the same time so that the block gives an output
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity threshold_extctl is
  generic(
    in_width      : natural := 8;
    default_value : natural := 0
    );
  port(
    clk          : in  std_logic;
    reset        : in  std_logic;
    data_in      : in  std_logic_vector(in_width-1 downto 0);
    data_in_enb  : in  std_logic;
    keep_in      : in  std_logic;
    keep_in_enb  : in  std_logic;
    data_out     : out std_logic_vector(in_width-1 downto 0);
    data_out_enb : out std_logic

    );
end threshold_extctl;


architecture rtl of threshold_extctl is

  -- Signals
  signal def_val : unsigned(in_width-1 downto 0);

begin

  def_val <= to_unsigned(default_value, in_width);

  threshold_process : process (clk, reset)
  begin
    if reset = '1' then

      data_out_enb <= '0';
      data_out     <= (others => '0');

    elsif rising_edge(clk) then

      data_out_enb <= '0';

      if data_in_enb = '1' and keep_in_enb = '1' then

        if keep_in = '1' then
          data_out <= data_in;
        else
          data_out <= std_logic_vector(def_val);
        end if;
        data_out_enb <= '1';
      end if;
    end if;
  end process threshold_process;

end rtl;