-------------------------------------------------------------------------------
--
--  File          : multadd_core.vhd
--  Related files : 
--
--  Author(s)     : stephane Domas (sdomas@univ-fcomte.fr)
--
--  Creation Date : 2015/04/27
--
--  Description   : This component is a multadd
--
--  Note          : No notes
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity multadd_core is
  generic (
    wb_data_width : integer := 16;
    wb_addr_width : integer := 12
    );
  port (
    -- clk/rst from multadd wrapper
    rst : in std_logic;
    clk : in std_logic;

    -- registers r/w via wishbone
    wb_do_op : in  std_logic;
    wb_c     : in  std_logic_vector(wb_data_width-1 downto 0);
    wb_d     : out std_logic_vector(2*wb_data_width-1 downto 0);

    -- data ports
    val1_i : in  std_logic_vector(17 downto 0);
    val2_i : in  std_logic_vector(17 downto 0);
    res_o : out std_logic_vector(35 downto 0)
    );
end multadd_core;


architecture multadd_core_1 of multadd_core is

     -- Signals
  signal a_s      : signed(17 downto 0);
  signal b_s      : signed(17 downto 0);
  signal c_s      : signed(35 downto 0);
  signal result   : signed(35 downto 0);

begin

  a_s <= signed(val1_i);
  b_s <= signed(val2_i);
  c_s <= resize(signed(wb_c),36);
  
  do_mult_process : process (clk, rst)
  begin
    if rst = '1' then
      
      result <= to_signed(0,36);
      
    elsif (rising_edge(clk)) then

      if wb_do_op = '1' then
        result <= a_s * b_s + c_s;
      end if;
      
    end if;
  end process do_mult_process;

  res_o <= std_logic_vector(result);
  wb_d <= std_logic_vector(resize(result,32);
  
end multadd_core_1;