OPT := params-isim.txt

include $(OPT)

ISIM_DIR := isim

ISIM_LIB := work

all : project compile 

project : $(PROJECT).prj

compile : $(PROJECT).prj $(VHDL_SRC)
	tb_name=$$( echo $(TB_SRC) | sed 's,.*/,,' | sed 's,[.].*,,'); \
	fuse $(ISIM_LIB).$$tb_name $(ISIM_LIB).glbl -prj $(PROJECT).prj -L unisim -L secureip -timeprecision_vhdl ps -o $(SIMU_EXE)

view :
	$(SIMU_EXE) -gui -wdb $(SIMU_EXE).wdb

$(PROJECT).prj :
	if [ -f $@ ]; then rm $@; fi
	echo "### VHDL sources"
	for fich in $(VHDL_SRC); do echo vhdl $(ISIM_LIB) $$fich >> $@; done
	echo "### verilog sources"
	for fich in $(VL_SRC); do echo verilog $(ISIM_LIB) $$fich >> $@; done
	echo "### test bench sources"
	for fich in $(TB_SRC); do echo vhdl $(ISIM_LIB) $$fich >> $@; done

clean :
	rm -f *~
	rm -f $(PROJECT).prj
	cd $(SRC_DIR); rm -f *~
	cd $(TB_DIR); rm -f *~