-------------------------------------------------------------------------------
--
--  File          : logical_AND_3.vhd
--  Related files : 
--
--  Author(s)     : stephane Domas (sdomas@univ-fcomte.fr)
--
--  Creation Date : 2017/10/16
--
--  Description   : This IP does a logical AND on three inputs.
--  
--
--  Note          :
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity logical_AND_3 is
  port(
    clk          : in  std_logic;
    reset        : in  std_logic;
    data1_in      : in  std_logic;
    data1_in_enb  : in  std_logic;
    data2_in      : in  std_logic;
    data2_in_enb  : in  std_logic;
    data3_in      : in  std_logic;
    data3_in_enb  : in  std_logic;
    
    data_out     : out std_logic;
    data_out_enb : out std_logic  -- the control signal, common to all output
    );
end logical_AND_3;


architecture rtl of logical_AND_3 is

begin

  and_process : process (clk, reset)
  begin
    if reset = '1' then

      data_out <= '0';
      data_out_enb    <= '0';

    elsif rising_edge(clk) then

      data_out <= '0';
      data_out_enb    <= '0';
      
      if data1_in_enb = '1' and data2_in_enb = '1' and data3_in_enb = '1' then
        
        data_out <= data1_in and data2_in and data3_in;
        data_out_enb <= '1';
        
      end if;
    end if;

  end process and_process;

end rtl;