-------------------------------------------------------------------------------
--
--  File          : checker.vhd
--  Related files : 
--
--  Author(s)     : stephane Domas (sdomas@univ-fcomte.fr)
--
--  Creation Date : 2017/10/16
--
--  Description   : This IP does a threshold on an input
--  
--
--  Note          : The  input is compared to one (or two) values and depending
--                  on the result and the type of the comparison, the check output
--                  is asserted to 1 or not.
--                  The values are fixed by generic parameter.
--                  The type of check is fixed by a generic paramter
--                  type 1 : test if lesser or equal than X
--                  type 2 : test if gretar or equal than X
--                  type 3 : test if greater or equal than X and lesser or equal than Y
--
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity checker is
  generic(
    in_width   : natural := 8;
    check_type : natural := 1;
    inf_value  : natural := 0;
    sup_value  : natural := 0
    );
  port(
    clk          : in  std_logic;
    reset        : in  std_logic;
    data_in      : in  std_logic_vector(in_width-1 downto 0);
    data_in_enb  : in  std_logic;
    data_out     : out std_logic_vector(in_width-1 downto 0);
    data_out_enb : out std_logic;
    check_out    : out std_logic;
    check_out_enb : out std_logic
    );
end checker;


architecture rtl of checker is

begin

  check_process : process (clk, reset)
  begin
    if reset = '1' then

      check_out    <= '0';
      data_out <= (others => '0');
      data_out_enb    <= '0';
      check_out_enb    <= '0';      

    elsif rising_edge(clk) then

      check_out    <= '0';
      data_out <= (others => '0');
      data_out_enb    <= '0';
      check_out_enb    <= '0';
      
      if data_in_enb = '1' then
        
        data_out <= data_in;
        data_out_enb <= '1';
        check_out_enb    <= '1';
        
        if check_type = 1 then
          if unsigned(data_in) <= inf_value then
            check_out <= '1';
          end if;          
        elsif check_type = 2 then
          if unsigned(data_in) >= inf_value then
            check_out <= '1';
          end if;          
        elsif check_type = 3 then
          if unsigned(data_in) >= inf_value and unsigned(data_in) <= sup_value then
            check_out <= '1';
          end if;                  
        end if;
      end if;
    end if;

  end process check_process;

end rtl;