-------------------------------------------------------------------------------
--
--  File          : deserializer_3x1.vhd
--  Related files : 
--
--  Author(s)     : stephane Domas (sdomas@univ-fcomte.fr)
--
--  Creation Date : 2017/10/16
--
--  Description   : This IP does a deserialization of 3 element into
--                  3 parallel outputs
--  
--
--  Note          : 
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity deserializer_3x1 is
  generic(
    in_width : natural := 8
    );
  port(
    clk           : in  std_logic;
    reset         : in  std_logic;
    data_in       : in  std_logic_vector(in_width-1 downto 0);
    data_in_enb   : in  std_logic;
    data1_out     : out std_logic_vector(in_width-1 downto 0);
    data1_out_enb : out std_logic;
    data2_out     : out std_logic_vector(in_width-1 downto 0);
    data2_out_enb : out std_logic;    
    data3_out     : out std_logic_vector(in_width-1 downto 0);
    data3_out_enb : out std_logic

    );
end deserializer_3x1;


architecture rtl of deserializer_3x1 is

  -- Signals
  signal do_out    : std_logic;
  signal data1_reg : std_logic_vector(in_width-1 downto 0);
  signal data2_reg : std_logic_vector(in_width-1 downto 0);

  signal count : unsigned(1 downto 0);

begin

  deser_process : process (clk, reset)
  begin
    if reset = '1' then
      count     <= to_unsigned(0, 2);
      data1_reg <= (others => '0');
      data2_reg <= (others => '0');
      data1_out <= (others => '0');
      data2_out <= (others => '0');
      data3_out <= (others => '0');
      do_out    <= '0';

    elsif rising_edge(clk) then

      do_out    <= '0';
      data1_out <= (others => '0');
      data2_out <= (others => '0');
      data3_out <= (others => '0');

      if data_in_enb = '1' then

        if count = 0 then
          data1_reg <= data_in;
          count     <= count + 1;
        elsif count = 1 then
          data2_reg <= data_in;
          count     <= count + 1;
        elsif count = 2 then
          data1_out <= data1_reg;
          data2_out <= data2_reg;
          data3_out <= data_in;
          do_out    <= '1';
          count     <= to_unsigned(0, 2);
        end if;
      end if;
    end if;

  end process deser_process;

  data1_out_enb <= do_out;
  data2_out_enb <= do_out;
  data3_out_enb <= do_out;  

end rtl;