started VHDL generation of GroupBlock

[blast.git] / GroupBlock.cpp

diff --git a/GroupBlock.cpp b/GroupBlock.cpp
index f618789b3528a2d3a8a3cfdd00f54131679c16e9..9a8bb0f857df75dd5843ad5069cc80aa27f852fb 100644 (file)
--- a/GroupBlock.cpp
+++ b/GroupBlock.cpp
@@ -311,11 +311,13 @@ void GroupBlock::generateLibraries(QTextStream& out, QDomElement &elt) throw(Exc
 
 }
 
-void GroupBlock::generateEntity(QTextStream& out, bool hasController) throw(Exception) {
+void GroupBlock::generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController) throw(Exception) {
 
   int i;
-
-  out << "entity " << name << " is " << endl;
+  QString indent = "";
+  for(i=0;i<indentLevel;i++) {
+    indent += " ";
+  }
 
   QList<BlockParameter*> listGenerics = getGenericParameters();
   QList<AbstractInterface*> listInputs = getInputs();
@@ -323,21 +325,21 @@ void GroupBlock::generateEntity(QTextStream& out, bool hasController) throw(Exce
   QList<AbstractInterface*> listBidirs = getBidirs();
 
   if (!listGenerics.isEmpty()) {
-    out << "  generic (" << endl;
+    out << indent << "  generic (" << endl;
     for(i=0;i<listGenerics.size()-1;i++) {
-      out << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
+      out << indent << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
     }
-    out << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
-    out << "    );" << endl;
+    out << indent << "    " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
+    out << indent << "    );" << endl;
   }
 
-  out << "  port (" << endl;
+  out << indent << "  port (" << endl;
 
   // Generation of the clk & rst signals
-  out << "    -- clk/rst" << endl;
+  out << indent << "    -- clk/rst" << endl;
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {
-      out << "    " << iface->getName() << " : in std_logic;" << endl;
+      out << indent << "    " << iface->getName() << " : in std_logic;" << endl;
     }
   }
 
@@ -353,69 +355,123 @@ void GroupBlock::generateEntity(QTextStream& out, bool hasController) throw(Exce
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
-        out << "    -- input data ports" << endl;
+        out << indent << "    -- input data ports" << endl;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listInputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {
-        out << "    -- input control ports" << endl;
+        out << indent << "    -- input control ports" << endl;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
-        out << "    -- output data ports" << endl;
+        out << indent << "    -- output data ports" << endl;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listOutputs) {
     if(iface->getPurpose() == AbstractInterface::Control) {
       if (first) {
-        out << "    -- output control ports" << endl;
+        out << indent << "    -- output control ports" << endl;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
     }
   }
   first = true;
   foreach(AbstractInterface* iface, listBidirs) {
     if(iface->getPurpose() == AbstractInterface::Data) {
       if (first) {
-        out << "    -- bidirs data ports" << endl;
+        out << indent << "    -- bidirs data ports" << endl;
         first = false;
       }
       count--;
       if (count == 0) flag = AbstractInterface::NoComma;
-      out << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+      out << indent << "    " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
     }
   }
-  out << "    );" << endl << endl;
-  out << "end " << name << ";" << endl << endl;
-
+  out << indent << "    );" << endl << endl;
 }
 
 void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(Exception) {
 
+  int i;
+
+  out << "architecture rtl of " << name << " is " << endl << endl;
+
+  // generate the components
+  foreach(AbstractBlock* block, blocks) {
+    try {
+      block->generateComponent(out,false);
+    }
+    catch(Exception e) {
+      throw(e);
+    }
+  }
+
+  out << endl;
+  // generate signals
+  out << "  ----------------------------" << endl;
+  out << "    SIGNALS" << endl;
+  out << "  ----------------------------" << endl << endl;
+
+  out << "  -- signals from input ports of " << name << endl;
+  QList<AbstractInterface*> listInputs = getInputs();
+  foreach(AbstractInterface* iface, listInputs) {
+    if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+      ConnectedInterface* connIface = AI_TO_CON(iface);
+      QString prefixName = name+"_"+iface->getName()+"_TO_";
+      foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) {
+        QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName();
+        out << "  signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+      }
+    }
+  }
+  out << endl;
+  foreach(AbstractBlock* block, blocks) {
+    try {
+      out << "  -- signals from output ports of " << block->getName() << endl;
+      QList<AbstractInterface*> listOutputs = block->getOutputs();
+      foreach(AbstractInterface* iface, listOutputs) {
+        if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+          ConnectedInterface* connIface = AI_TO_CON(iface);
+          QString prefixName = block->getName()+"_"+iface->getName()+"_TO_";
+          foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) {
+            QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName();
+            out << "  signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+          }
+        }
+      }
+    }
+    catch(Exception e) {
+      throw(e);
+    }
+    out << endl;
+  }
+
+
+  out << "end architecture rtl;" << endl;
 }
 
 void GroupBlock::generateController(QTextStream &out) throw(Exception) {