}\r
}\r
\r
-void FunctionalBlock::generateEntity(QTextStream& out, bool hasController) throw(Exception) {\r
+\r
+void FunctionalBlock::generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController) throw(Exception) {\r
\r
int i=0;\r
+ QString indent = "";\r
+ for(i=0;i<indentLevel;i++) {\r
+ indent += " ";\r
+ }\r
\r
//QList<BlockParameter*> listParams = reference->getParameters();\r
QList<AbstractInterface*> listInputs = getInputs();\r
QList<AbstractInterface*> listOutputs = getOutputs();\r
- QList<AbstractInterface*> listBidirs = getBidirs();\r
- QString typePort, namePort;\r
-\r
- out << "entity " << name << " is" << endl;\r
-\r
-\r
- /* TODO : rewrite the generation to take into acocunt the new object hierarchy */\r
+ QList<AbstractInterface*> listBidirs = getBidirs(); \r
\r
// Generation of the generics\r
QList<BlockParameter*> listGenerics = getGenericParameters();\r
if ((!listGenerics.isEmpty()) || (hasController)) {\r
- out << " generic (" << endl;\r
+ out << indent << " generic (" << endl;\r
if (hasController) {\r
- out << " wb_data_width : integer = 16;" << endl;\r
- out << " wb_addr_width : integer = 12";\r
- if (!listGenerics.isEmpty()) out << ";";\r
+ out << indent << " wb_data_width : integer = 16;" << endl;\r
+ out << indent << " wb_addr_width : integer = 12";\r
+ if (!listGenerics.isEmpty()) out << indent << ";";\r
out << endl;\r
}\r
for(i=0;i<listGenerics.size()-1;i++) {\r
- out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
+ out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
}\r
- out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
+ out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
\r
- out << " );" << endl;\r
+ out << indent << " );" << endl;\r
}\r
\r
- out << " port (" << endl;\r
+ out << indent << " port (" << endl;\r
\r
// Generation of the clk & rst signals\r
- out << " -- clk/rst" << endl;\r
+ out << indent << " -- clk/rst" << endl;\r
foreach(AbstractInterface* iface, listInputs) {\r
if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
- out << " " << iface->getName() << " : in std_logic;" << endl;\r
+ out << indent << " " << iface->getName() << " : in std_logic;" << endl;\r
+ }\r
+ }\r
+ foreach(AbstractInterface* iface, listOutputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
+ out << indent << " " << iface->getName() << " : out std_logic;" << endl;\r
}\r
}\r
\r
if (hasController) {\r
// Generation of the wishbone signals\r
- out << " -- registers r/w via wishbone" << endl;\r
+ out << indent << " -- registers r/w via wishbone" << endl;\r
QList<BlockParameter*> listWB = reference->getWishboneParameters();\r
for(i=0;i<listWB.size()-1;i++) {\r
- out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
+ out << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
}\r
- out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
+ out << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
}\r
\r
\r
foreach(AbstractInterface* iface, listInputs) {\r
if(iface->getPurpose() == AbstractInterface::Data) {\r
if (first) {\r
- out << " -- input data ports" << endl;\r
+ out << indent << " -- input data ports" << endl;\r
first = false;\r
}\r
count--;\r
if (count == 0) flag = AbstractInterface::NoComma;\r
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
}\r
}\r
first = true;\r
foreach(AbstractInterface* iface, listInputs) {\r
if(iface->getPurpose() == AbstractInterface::Control) {\r
if (first) {\r
- out << " -- input control ports" << endl;\r
+ out << indent << " -- input control ports" << endl;\r
first = false;\r
}\r
count--;\r
if (count == 0) flag = AbstractInterface::NoComma;\r
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
}\r
}\r
first = true;\r
foreach(AbstractInterface* iface, listOutputs) {\r
if(iface->getPurpose() == AbstractInterface::Data) {\r
if (first) {\r
- out << " -- output data ports" << endl;\r
+ out << indent << " -- output data ports" << endl;\r
first = false;\r
}\r
count--;\r
if (count == 0) flag = AbstractInterface::NoComma;\r
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
}\r
}\r
first = true;\r
foreach(AbstractInterface* iface, listOutputs) {\r
if(iface->getPurpose() == AbstractInterface::Control) {\r
if (first) {\r
- out << " -- output control ports" << endl;\r
+ out << indent << " -- output control ports" << endl;\r
first = false;\r
}\r
count--;\r
if (count == 0) flag = AbstractInterface::NoComma;\r
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
}\r
}\r
first = true;\r
foreach(AbstractInterface* iface, listBidirs) {\r
if(iface->getPurpose() == AbstractInterface::Data) {\r
if (first) {\r
- out << " -- bidirs data ports" << endl;\r
+ out << indent << " -- bidirs data ports" << endl;\r
first = false;\r
}\r
count--;\r
if (count == 0) flag = AbstractInterface::NoComma;\r
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
}\r
}\r
- out << " );" << endl << endl;\r
- out << "end " << name << ";" << endl << endl;\r
+ out << indent << " );" << endl << endl;\r
+\r
}\r
\r
void FunctionalBlock::generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception) {\r
