finished testbench generation

[blast.git] / Makefile-isim

diff --git a/Makefile-isim b/Makefile-isim
index c10eb1d14e3f7c956a576057c68d96b52b20fa6b..15319a141e556cd6f3d14c8342fde545e8be9241 100644 (file)
--- a/Makefile-isim
+++ b/Makefile-isim
@@ -8,16 +8,16 @@ ISIM_LIB := work
 
 all : project compile 
 
-project : $(PROJECT).prj
+project : $(PROJECT_NAME).prj
 
-compile : $(PROJECT).prj $(VHDL_SRC)
+compile : $(PROJECT_NAME).prj $(VHDL_SRC)
        tb_name=$$( echo $(TB_SRC) | sed 's,.*/,,' | sed 's,[.].*,,'); \
-       fuse $(ISIM_LIB).$$tb_name $(ISIM_LIB).glbl -prj $(PROJECT).prj -L unisim -L secureip -timeprecision_vhdl ps -o $(SIMU_EXE)
+       fuse $(ISIM_LIB).$$tb_name $(ISIM_LIB).glbl -prj $(PROJECT_NAME).prj -L unisim -L secureip -timeprecision_vhdl ps -o $(SIMU_EXE)
 
 view :
        $(SIMU_EXE) -gui -wdb $(SIMU_EXE).wdb
 
-$(PROJECT).prj :
+$(PROJECT_NAME).prj :
        if [ -f $@ ]; then rm $@; fi
        echo "### VHDL sources"
        for fich in $(VHDL_SRC); do echo vhdl $(ISIM_LIB) $$fich >> $@; done
@@ -28,6 +28,6 @@ $(PROJECT).prj :
 
 clean :
        rm -f *~
-       rm -f $(PROJECT).prj
+       rm -f $(PROJECT_NAME).prj
        cd $(SRC_DIR); rm -f *~
        cd $(TB_DIR); rm -f *~