int GroupBlock::counter = 1;
-GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) : AbstractBlock() {
+GroupBlock::GroupBlock(GroupBlock *_parent, bool createIfaces) throw(Exception) : AbstractBlock() {
GroupInterface* clk = NULL;
GroupInterface* rst = NULL;
out << " -- SIGNALS" << endl;
out << " ----------------------------" << endl << endl;
-// "normal" signals
+ // signals to synchronize inputs
+ out << " -- signals to synchronize inputs" << endl;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ QString name = iface->toVHDL(AbstractInterface::Signal,0);
+ name.replace(" : ","_sync : ");
+ out << " signal " << name<< endl;
+ }
+ }
+ out << endl;
+
+ // "normal" signals
foreach(AbstractBlock* block, blocks) {
try {
out << " -- signals from output ports of " << block->getName() << endl;
}
}
else if (fromIface->isGroupInterface()) {
- portMap += " " + connIface->getName() + " => " + fromIface->getName() + ",\n";
+ if ((fromIface->getOwner()->isTopGroupBlock()) && ((fromIface->getPurpose() == AbstractInterface::Data)||(fromIface->getPurpose() == AbstractInterface::Control))) {
+ portMap += " " + connIface->getName() + " => " + fromIface->getOwner()->getName()+ "_"+ fromIface->getName() + "_sync,\n";
+ }
+ else {
+ portMap += " " + connIface->getName() + " => " + fromIface->getName() + ",\n";
+ }
}
}
if (listOutputs.size()>0) {
}
}
+ if (topGroup) {
+ // generate input sync process
+ out << " -- process to synchronize inputs of top group" << endl;
+ out << "sync_inputs : process(from_clkrstgen_clk,from_clkrstgen_reset)" << endl;
+ out << " begin" << endl;
+ out << " if from_clkrstgen_reset = '1' then" << endl;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ if (iface->getWidth() == 0) {
+ out << " " << name << "_" << iface->getName() << "_sync <= '0';" << endl;
+ }
+ else {
+ out << " " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl;
+ }
+ }
+ }
+ out << " elsif rising_edge(from_clkrstgen_clk) then" << endl;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ if (iface->getWidth() == 0) {
+ out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+ }
+ else {
+ out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+ }
+ }
+ }
+ out << " end if;" << endl;
+ out << " end process sync_inputs;" << endl;
+
+ out << endl;
+ }
+
out << "end architecture rtl;" << endl;
}