int GroupBlock::counter = 1;
-GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) : AbstractBlock() {
+GroupBlock::GroupBlock(GroupBlock *_parent, bool createIfaces) throw(Exception) : AbstractBlock() {
+ parent = _parent;
GroupInterface* clk = NULL;
GroupInterface* rst = NULL;
// force topGroup to false if this group has a parent
- if (_parent != NULL) {
+ if (parent != NULL) {
topGroup = false;
name = QString("sub_group")+"_"+QString::number(counter++);
- // creating clk/rst interfaces
- clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock);
- rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset);
- addInterface(clk);
- addInterface(rst);
-
- try {
- connectClkReset();
- }
- catch(Exception e) {
- AbstractBlock* source = (AbstractBlock *)(e.getSource());
- cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl;
- throw(e);
- }
}
else {
topGroup = true;
name = QString("top_group");
// creating external clk/rst interfaces
- clk = new GroupInterface(this,"ext_clk", AbstractInterface::Input, AbstractInterface::Clock);
- rst = new GroupInterface(this,"ext_reset", AbstractInterface::Input, AbstractInterface::Reset);
- addInterface(clk);
- addInterface(rst);
- // creating clkrstgen block and connecting it to this: done in Dispatcher since this has no access to library
}
- parent = _parent;
- if (_parent != NULL) {
- try {
- connectClkReset();
+ if (createIfaces) {
+ if (topGroup) {
+ clk = new GroupInterface(this,"ext_clk_0", AbstractInterface::Input, AbstractInterface::Clock);
+ rst = new GroupInterface(this,"ext_reset_0", AbstractInterface::Input, AbstractInterface::Reset);
+ addInterface(clk);
+ addInterface(rst);
}
- catch(Exception e) {
- AbstractBlock* source = (AbstractBlock *)(e.getSource());
- cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl;
- throw(e);
+ else {
+ // get all clock and reset from parent
+ QList<AbstractInterface*> lstClk = parent->getInterfaces(AbstractInterface::Input, AbstractInterface::Clock);
+ QList<AbstractInterface*> lstRst = parent->getInterfaces(AbstractInterface::Input, AbstractInterface::Reset);
+ foreach(AbstractInterface* iface, lstClk) {
+ clk = new GroupInterface(this,iface->getName(),AbstractInterface::Input, AbstractInterface::Clock);
+ addInterface(clk);
+ }
+ foreach(AbstractInterface* iface, lstRst) {
+ rst = new GroupInterface(this,iface->getName(),AbstractInterface::Input, AbstractInterface::Reset);
+ addInterface(rst);
+ }
}
}
-
}
GroupBlock::~GroupBlock() {
}
void GroupBlock::computeAdmittanceDelays() throw(Exception) {
- throw(Exception(INVALID_GROUPBLOCK_USE));
+ throw(Exception(INVALID_GROUPBLOCK_USE,this));
}
void GroupBlock::checkInputPatternCompatibility() throw(Exception){
- throw(Exception(INVALID_GROUPBLOCK_USE));
+ throw(Exception(INVALID_GROUPBLOCK_USE,this));
}
bool addIt = false;
// if a block is a generator and has control outputs, add it
- if (block->isGeneratorBlock()) {
+ if (block->isSourceBlock()) {
if (block->getControlOutputs().size() > 0) addIt = true;
}
else {
while (!fifo.isEmpty()) {
AbstractBlock* block = fifo.takeFirst();
- if (block->getPatternComputed()) continue; // block has already been processed
+ if (block->getOutputPatternComputed()) continue; // block has already been processed
cout << "computing compat and output for " << qPrintable(block->getName()) << endl;
throw(e);
}
canCompute = true;
- block->setPatternComputed(true);
+
/* add other blocks connected from block to the fifo but only if
all their connected inputs are connected to blocks that have
a traversalLevel >=0
ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
//cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
- if ((connFrom != NULL) && (connFrom->getOwner()->getPatternComputed() == false)) {
+ if ((connFrom != NULL) && (connFrom->getOwner()->getOutputPatternComputed() == false)) {
addIt = false;
break;
}
QList<char>* pattern = new QList<char>(*(connIface->getConnectedFrom()->getOutputPattern()));
connIface->setOutputPattern(pattern);
}
- setPatternComputed(true);
+ setOutputPatternComputed(true);
}
}
out << " -- SIGNALS" << endl;
out << " ----------------------------" << endl << endl;
-// "normal" signals
+ // signals to synchronize inputs
+ out << " -- signals to synchronize inputs" << endl;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ QString name = iface->toVHDL(AbstractInterface::Signal,0);
+ name.replace(" : ","_sync : ");
+ out << " signal " << name<< endl;
+ }
+ }
+ out << endl;
+
+ // "normal" signals
foreach(AbstractBlock* block, blocks) {
try {
out << " -- signals from output ports of " << block->getName() << endl;
}
}
else if (fromIface->isGroupInterface()) {
- portMap += " " + connIface->getName() + " => " + fromIface->getName() + ",\n";
+ if ((fromIface->getOwner()->isTopGroupBlock()) && ((fromIface->getPurpose() == AbstractInterface::Data)||(fromIface->getPurpose() == AbstractInterface::Control))) {
+ portMap += " " + connIface->getName() + " => " + fromIface->getOwner()->getName()+ "_"+ fromIface->getName() + "_sync,\n";
+ }
+ else {
+ portMap += " " + connIface->getName() + " => " + fromIface->getName() + ",\n";
+ }
}
}
if (listOutputs.size()>0) {
}
}
+ if (topGroup) {
+ // generate input sync process
+ out << " -- process to synchronize inputs of top group" << endl;
+ out << "sync_inputs : process(from_clkrstgen_clk,from_clkrstgen_reset)" << endl;
+ out << " begin" << endl;
+ out << " if from_clkrstgen_reset = '1' then" << endl;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ if (iface->getWidth() == 0) {
+ out << " " << name << "_" << iface->getName() << "_sync <= '0';" << endl;
+ }
+ else {
+ out << " " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl;
+ }
+ }
+ }
+ out << " elsif rising_edge(from_clkrstgen_clk) then" << endl;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ if (iface->getWidth() == 0) {
+ out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+ }
+ else {
+ out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+ }
+ }
+ }
+ out << " end if;" << endl;
+ out << " end process sync_inputs;" << endl;
+
+ out << endl;
+ }
+
out << "end architecture rtl;" << endl;
}
