+ if (topGroup) {
+ // generate input sync process for each clock domain
+ out << " -- process to synchronize inputs of top group" << endl;
+ for(int i=0;i<graph->getClocks().size();i++) {
+ // check if there are some inputs that must be sync with clock domain i
+ bool mustSync = false;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ if (iface->getClockDomain() == i) {
+ mustSync = true;
+ break;
+ }
+ }
+ }
+ if (mustSync) {
+ out << "sync_inputs_" << i << " : process(from_clkrstgen_" << i << "_clk,from_clkrstgen_" << i << "_reset)" << endl;
+ out << " begin" << endl;
+ out << " if from_clkrstgen_" << i << "_reset = '1' then" << endl;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ if (iface->getClockDomain() == i) {
+ if (iface->getWidth() == 0) {
+ out << " " << name << "_" << iface->getName() << "_sync <= '0';" << endl;
+ }
+ else {
+ out << " " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl;
+ }
+ }
+ }
+ }
+ out << " elsif rising_edge(from_clkrstgen_" << i << "_clk) then" << endl;
+ foreach(AbstractInterface* iface, getInputs()) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ if (iface->getClockDomain() == i) {
+ if (iface->getWidth() == 0) {
+ out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+ }
+ else {
+ out << " " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+ }
+ }
+ }
+ }
+ out << " end if;" << endl;
+ out << " end process sync_inputs_" << i << ";" << endl;
+
+ out << endl;
+ }
+ }
+ }
+