finished testbench generation

[blast.git] / DelayInputModifier.cpp

diff --git a/DelayInputModifier.cpp b/DelayInputModifier.cpp
index a60d7e27a23440da0f40c862a33e892317eda7b9..242547c1e05ee9d854adfc772cb73b92253afa39 100644 (file)
--- a/DelayInputModifier.cpp
+++ b/DelayInputModifier.cpp
@@ -29,16 +29,17 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {
   ConnectedInterface* toIface = AI_TO_CON(toCtlIface->getAssociatedIface());\r
   QString toName = toIface->getOwner()->getName()+"_"+toIface->getName();\r
   QString toCtlName = toCtlIface->getOwner()->getName()+"_"+toCtlIface->getName();\r
-  QString dm1 = "";\r
   QString dm2 = "";\r
-  dm1.setNum(delayLength-1);\r
+  QString dm3 = "";\r
   dm2.setNum(delayLength-2);\r
+  dm3.setNum(delayLength-3);\r
   QString ret="";\r
-  QString clkName = "clk";\r
-  QString resetName = "reset";\r
+  int idClock = toIface->getClockDomain();\r
+  QString clkName = "ext_clk_"+QString::number(idClock);\r
+  QString resetName = "ext_reset_"+QString::number(idClock);\r
   if (toIface->getOwner()->getParent()->isTopGroupBlock()) {\r
-    clkName = "from_clkrstgen_clk";\r
-    resetName ="from_clkrstgen_reset";\r
+    clkName = "from_clkrstgen_"+QString::number(idClock)+"_clk";\r
+    resetName ="from_clkrstgen_"+QString::number(idClock)+"_reset";\r
   }\r
 \r
   if (context == Architecture) {\r
@@ -50,12 +51,12 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {
     ret += "      "+toName+"_mod     <= (others => '0');\n";\r
     ret += "      "+toCtlName+"_mod  <= '0';\n";\r
     ret += "    elsif rising_edge("+clkName+") then\n";\r
-    ret += "      "+toName+"_mod <= "+toName+"_dly("+dm1+");\n";\r
-    ret += "      "+toCtlName+"_mod  <= "+toCtlName+"_dly("+dm1+");\n";\r
+    ret += "      "+toName+"_mod <= "+toName+"_dly("+dm2+");\n";\r
+    ret += "      "+toCtlName+"_mod  <= "+toCtlName+"_dly("+dm2+");\n";\r
     ret += "      "+toName+"_dly(0)  <= "+fromIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
     ret += "      "+toCtlName+"_dly(0)  <= "+fromCtlIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
-    ret += "      "+toName+"_dly(1 to "+dm1+")  <= "+toName+"_dly(0 to "+dm2+");\n";\r
-    ret += "      "+toCtlName+"_dly(1 to "+dm1+")  <= "+toCtlName+"_dly(0 to "+dm2+");\n";\r
+    ret += "      "+toName+"_dly(1 to "+dm2+")  <= "+toName+"_dly(0 to "+dm3+");\n";\r
+    ret += "      "+toCtlName+"_dly(1 to "+dm2+")  <= "+toCtlName+"_dly(0 to "+dm3+");\n";\r
     ret += "    end if;\n";\r
     ret += "  end process "+toName + "_mod_process;\n";\r
   }\r
@@ -68,8 +69,8 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {
     ret += "  signal "+sig+"\n";\r
     QString wStr="";\r
     wStr.setNum(toIface->getWidth());\r
-    ret += "  signal "+toName+"_dly :  vector_of_std_logic_vector"+wStr+"(0 to "+dm1+");\n";\r
-    ret += "  signal "+toCtlName+"_dly :  vector_of_std_logic(0 to "+dm1+");\n";\r
+    ret += "  signal "+toName+"_dly :  vector_of_std_logic_vector"+wStr+"(0 to "+dm2+");\n";\r
+    ret += "  signal "+toCtlName+"_dly :  vector_of_std_logic(0 to "+dm2+");\n";\r
   }\r
 \r
   return ret;\r