enum IfaceDirection { AnyDirection = 0, Input = 1, Output = 2, InOut = 3 };
enum IfaceVHDLContext {AnyContext = 0, Entity = 1, Component = 2, Instance = 3, Signal = 4 };
enum IfaceVHDLFlags { NoComma = 1 };
+ enum IfaceClockName { NoName = 0, ClockName, ParameterName };
static int getIntDirection(QString str);
static int getIntPurpose(QString str);
QString getDirectionString();
inline AbstractBlock *getOwner() { return owner;}
inline AbstractInterface* getAssociatedIface() { return associatedIface; }
+ inline QString getClockIfaceString() { return clkIface; }
+ inline int getClockIfaceType() { return clkIfaceType; }
+ AbstractInterface* getClockIface();
+
double getDoubleWidth() throw(QException);
void setPurpose(int _purpose);
void setDirection(int _direction);
bool setAssociatedIface(AbstractInterface* iface);
+ bool setClockIface(QString name);
// testers
virtual bool isReferenceInterface();
* (NB: a test is done in the method to prevent the other case).
*/
AbstractInterface* associatedIface;
+ /*!
+ * \brief clkIface represents the clock interface that is used in processes modifying this interface. It is only relevant for
+ * Data interfaces and clock outputs (that comes from a clkrstgen). Since Control interfaces are automatically associated to a
+ * Data interface, clkIface is "" for them. Wishbone interfaces
+ * In general, blocks have a single
+ * clock interface which is by default automatically connected to the main clock dispatched by the clkrstgen block in top group.
+ * Nevertheless, the designer has the possibility to connect the block taht owns this interface to another clkrstgen block. Moreover,
+ * some blocks may have several clocks, e.g. dual port RAMs, FIFOs.
+ */
+ QString clkIface;
+ int clkIfaceType; // 0 for not affected, 1 for clock input name, 2 for user param name
};
