finalized analysis with clkconvert + started testbench gen.

[blast.git] / lib / implementations / clkdomain_convert_1024x8_impl.xml

diff --git a/lib/implementations/clkdomain_convert_1024x8_impl.xml b/lib/implementations/clkdomain_convert_1024x8_impl.xml
index f5c5ead27aed7c68060bac6f64d722095e434a15..6046ebea0be755346aab416143e088acbc908df5 100644 (file)
--- a/lib/implementations/clkdomain_convert_1024x8_impl.xml
+++ b/lib/implementations/clkdomain_convert_1024x8_impl.xml
@@ -37,8 +37,8 @@ begin
 clkdconvert_1024x8_1 : clkdconvert_1024x8
 port map (
 rst => @{reset},
 clkdconvert_1024x8_1 : clkdconvert_1024x8
 port map (
 rst => @{reset},

-wr_clk => @{clk_wr},
-rd_clk => @{clk_rd},
+wr_clk => @{clk_in},
+rd_clk => @{clk_out},

 din => @{data_in},
 wr_en => @{data_in_enb},
 rd_en => rd_en,
 din => @{data_in},
 wr_en => @{data_in_enb},
 rd_en => rd_en,


@@ -49,11 +49,11 @@ empty => empty
 
 rd_en <= not empty;
 
 
 rd_en <= not empty;
 

-read_fifo : process(@{clk_rd}, @{reset})
+read_fifo : process(@{clk_out}, @{reset})

 begin
 if @{reset} = '1' then
 @{data_out_enb} <= '0';
 begin
 if @{reset} = '1' then
 @{data_out_enb} <= '0';

-elsif rising_edge(@{clk_rd}) then
+elsif rising_edge(@{clk_out}) then

 @{data_out_enb} <= '0';
 if empty = '0' then
 @{data_out_enb} <= '1';
 @{data_out_enb} <= '0';
 if empty = '0' then
 @{data_out_enb} <= '1';