finished testbench generation

[blast.git] / lib / implementations / clkdomain_convert_1024x8_impl.xml

diff --git a/lib/implementations/clkdomain_convert_1024x8_impl.xml b/lib/implementations/clkdomain_convert_1024x8_impl.xml
index f5c5ead27aed7c68060bac6f64d722095e434a15..aa35dfe5c29a8ff0e2833ec6cca28ce499647a61 100644 (file)
--- a/lib/implementations/clkdomain_convert_1024x8_impl.xml
+++ b/lib/implementations/clkdomain_convert_1024x8_impl.xml
@@ -37,8 +37,8 @@ begin
 clkdconvert_1024x8_1 : clkdconvert_1024x8
 port map (
 rst => @{reset},
-wr_clk => @{clk_wr},
-rd_clk => @{clk_rd},
+wr_clk => @{clk_in},
+rd_clk => @{clk_out},
 din => @{data_in},
 wr_en => @{data_in_enb},
 rd_en => rd_en,
@@ -49,19 +49,17 @@ empty => empty
 
 rd_en <= not empty;
 
-read_fifo : process(@{clk_rd}, @{reset})
+read_fifo : process(@{clk_out}, @{reset})
 begin
 if @{reset} = '1' then
 @{data_out_enb} <= '0';
-elsif rising_edge(@{clk_rd}) then
+elsif rising_edge(@{clk_out}) then
 @{data_out_enb} <= '0';
 if empty = '0' then
 @{data_out_enb} <= '1';
 end if;
 end if;
 end process read_fifo;
-
-end architecture clkdomain_convert_1024x8_1;
 </architecture>
   <patterns>
     <delta value="1"/>