finalized analysis with clkconvert + started testbench gen.

[blast.git] / Dispatcher.cpp

diff --git a/Dispatcher.cpp b/Dispatcher.cpp
index e1857c326c27322dcbf0a915c0b83bf215916a53..266160b12b4eba2a89824487e44f911c00095eec 100644 (file)
--- a/Dispatcher.cpp
+++ b/Dispatcher.cpp
@@ -118,15 +118,16 @@ bool Dispatcher::createConnection(Context context, InterfaceItem *iface1, Interf
     ref2->connectTo(ref1);    
     ok2 = true;
   }
-  if ((ok1 == true) || (ok2 == true)) {
-
-    cout << "trying to create a connection from " << qPrintable(ref1->getOwner()->getName()) << "/" << qPrintable(ref1->getName());
-    cout << " to " << qPrintable(ref2->getOwner()->getName()) << "/" << qPrintable(ref2->getName());
+  if ((ok1 == true) || (ok2 == true)) {    
 
     if (ok1) {
+      cout << "trying to create a connection from " << qPrintable(ref1->getOwner()->getName()) << "/" << qPrintable(ref1->getName());
+      cout << " to " << qPrintable(ref2->getOwner()->getName()) << "/" << qPrintable(ref2->getName());
       iface1->getOwner()->getScene()->createConnectionItem(iface1,iface2, visible);
     }
     else {
+      cout << "trying to create a connection from " << qPrintable(ref2->getOwner()->getName()) << "/" << qPrintable(ref2->getName());
+      cout << " to " << qPrintable(ref1->getOwner()->getName()) << "/" << qPrintable(ref1->getName());
       iface2->getOwner()->getScene()->createConnectionItem(iface2,iface1, visible);
     }
 
@@ -223,10 +224,10 @@ void Dispatcher::generateVHDL(Context context) throw(Exception) {
     make.copy(dest);
   }
 
-  // copying external resources
+  // generate VHDL + copying external resources
   QString dest = params->projectPath;
-  dest += "/src/";
-  try {
+  dest += "/src/";  
+  try {    
     params->getGraph()->generateVHDL(dest);
 
     QList<QString> extResources = params->getGraph()->getExternalResources();
@@ -245,6 +246,17 @@ void Dispatcher::generateVHDL(Context context) throw(Exception) {
   catch(Exception e) {
     throw(e);
   }
+  // generate testbench
+  dest = params->projectPath;
+  dest += "/testbench/";
+  dest += params->projectName;
+  dest += "_tb.vhd";
+  try {
+    params->getGraph()->generateTestbench(params->projectName, dest);
+  }
+  catch(Exception e) {
+    throw(e);
+  }
 
   // creating parameters file
   QString paramName = params->projectPath+"/params-isim.txt";
@@ -273,8 +285,7 @@ void Dispatcher::generateVHDL(Context context) throw(Exception) {
   }
   out << endl;
   out << "VL_SRC := ${XILINX}/verilog/src/glbl.v" << endl << endl;
-  out << "TB_SRC := $(TB_DIR)/read_csv.vhd \\" << endl;
-  out << "\t$(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl;
+  out << "TB_SRC := $(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl;
   out << "SIMU_EXE := $(PROJECT_NAME)_tb" << endl << endl;
 
   paramFile.close();
@@ -759,13 +770,16 @@ GroupWidget *Dispatcher::createTopScene(Context context, double mainClock){
   cout << "call to " << qPrintable(fctName) << endl;
 #endif
 
-  bool createIfaces = true;
-  if (context == Load) {
-    createIfaces = false;
-  }
+  Graph* graph = NULL;
   // creating the graph and thus, the topgroup
-  Graph* graph = params->initGraph(createIfaces);
-  graph->addClock(mainClock);
+  if (context == Design) {
+    graph = params->initGraph(true);
+    graph->addClock(mainClock);
+  }
+  else if (context == Load) {
+    graph = params->initGraph(false);
+  }
+
   // get the top group
   GroupBlock *topBlock = graph->getTopGroup();
   // creating the top group widget