finalized analysis with clkconvert + started testbench gen.

[blast.git] / Graph.cpp

diff --git a/Graph.cpp b/Graph.cpp
index 808dbda2f18486c8e247651e4290cea3fdebd109..d0c11cc30907263705db2dc8521183dab7d9ea35 100644 (file)
--- a/Graph.cpp
+++ b/Graph.cpp
@@ -46,7 +46,7 @@ GroupBlock* Graph::getGroupBlockByName(QString name) {
 FunctionalBlock* Graph::createFunctionalBlock(GroupBlock* group, ReferenceBlock* ref, bool createIfaces) {
 
   FunctionalBlock* newBlock = NULL;
 FunctionalBlock* Graph::createFunctionalBlock(GroupBlock* group, ReferenceBlock* ref, bool createIfaces) {
 
   FunctionalBlock* newBlock = NULL;

-  if (ref->getSpecialType() != -1) {
+  if (ref->getSpecialType() != SpecialBlock::NotSpecial) {

     cout << "Graph: create special block from " << qPrintable(ref->getName()) << endl;
     newBlock = new SpecialBlock(this, ref->getSpecialType(), group,ref, createIfaces);
   }
     cout << "Graph: create special block from " << qPrintable(ref->getName()) << endl;
     newBlock = new SpecialBlock(this, ref->getSpecialType(), group,ref, createIfaces);
   }


@@ -206,6 +206,18 @@ void Graph::computeOutputPatterns(int nbExec) throw(Exception) {
 }
 
 void Graph::generateVHDL(const QString &path) throw(Exception) {
 }
 
 void Graph::generateVHDL(const QString &path) throw(Exception) {

+  // generating VHDL for stimulis
+  cout << "generating stimulis" << endl;
+  try {
+    foreach(FunctionalBlock* stimuli, stimulis) {
+      stimuli->generateVHDL(path);
+    }
+  }
+  catch(Exception e) {
+    throw(e);
+  }
+  // generating VHDL for top group
+  cout << "generating top group" << endl;

   try {
     topGroup->generateVHDL(path);
   }
   try {
     topGroup->generateVHDL(path);
   }


@@ -214,6 +226,72 @@ void Graph::generateVHDL(const QString &path) throw(Exception) {
   }
 }
 
   }
 }
 

+void Graph::generateTestbench(const QString &projectName, const QString &benchFile) throw(Exception) {
+
+
+  QFile vhdlBench(benchFile);
+
+  if (!vhdlBench.open(QIODevice::WriteOnly)) {
+    throw(Exception(VHDLFILE_NOACCESS));
+  }
+
+  cout << "generate testbench" << endl;
+  QTextStream out(&vhdlBench);
+
+  out << "-------------------------------------------------------------------------------" << endl;
+  out << "-- testbench for " << projectName << endl;
+  out << "-------------------------------------------------------------------------------" << endl << endl;
+  out << "-------------------------------------------------------------------------------" << endl;
+  out << "-- clock generator" << endl;
+  out << "-------------------------------------------------------------------------------" << endl << endl;
+
+  out << "library IEEE;" << endl;
+  out << "use IEEE.STD_LOGIC_1164.all;" << endl;
+  out << "use IEEE.numeric_std.all;" << endl;
+  out << "entity clock_gen is" << endl;
+  out << "  generic (" << endl;
+  out << "    Tps : time                          -- high level width : must be < period" << endl;
+  out << "    );" << endl;
+  out << "  port (" << endl;
+  out << "    phase : out std_logic" << endl;
+  out << "    );" << endl;
+  out << "end entity clock_gen;"  << endl<< endl;
+
+  out << "architecture clock_gen_1 of clock_gen is" << endl;
+  out << "  constant period : time := 2*Tps;" << endl;
+  out << "begin" << endl;
+  out << "  clock_process : process" << endl;
+  out << "  begin" << endl;
+  out << "    phase <= '1', '0' after Tps;" << endl;
+  out << "    wait for period;" << endl;
+  out << "  end process clock_process;" << endl;
+  out << "end architecture clock_gen_1;" << endl << endl;
+
+  out << "-------------------------------------------------------------------------------" << endl;
+  out << "-- testbench" << endl;
+  out << "-------------------------------------------------------------------------------" << endl << endl;
+  out << "library IEEE;" << endl;
+  out << "use IEEE.STD_LOGIC_1164.all;" << endl;
+  out << "use IEEE.numeric_std.all;" << endl;
+  out << "entity " << projectName << "_tb is" << endl;
+  out << "end entity " << projectName << "_tb;" << endl << endl;
+  out << "architecture " << projectName << "_tb_1 of " << projectName << "_tb is" << endl << endl;
+
+  out << "  component clock_gen" << endl;
+  out << "    generic (" << endl;
+  out << "      Tps : time" << endl;
+  out << "      );" << endl;
+  out << "    port (" << endl;
+  out << "      phase : out std_logic" << endl;
+  out << "      );" << endl;
+  out << "  end component;" << endl << endl;
+
+  topGroup->generateComponent(out,false);
+
+  vhdlBench.close();
+
+}
+

 QList<QString> Graph::getExternalResources() {
   QList<QString> list = topGroup->getExternalResources();
   return list;
 QList<QString> Graph::getExternalResources() {
   QList<QString> list = topGroup->getExternalResources();
   return list;