finalized analysis with clkconvert + started testbench gen.

[blast.git] / lib / references / apf27-wb-master.xml

diff --git a/lib/references/apf27-wb-master.xml b/lib/references/apf27-wb-master.xml
index 97300cd2ab46eef1c5e38b27521872d3b1538808..781914cb507a295fcb77bfddb565bd5931af8f91 100644 (file)
--- a/lib/references/apf27-wb-master.xml
+++ b/lib/references/apf27-wb-master.xml
@@ -2,20 +2,16 @@
 <block>
   <informations>
     <name>
-      wishbone master for apf27
+      apf27_wb_master
     </name>
-    <category ids="1,4" />  
+    <category ids="8" />  
     <description>
-      <brief>
        This block is the wishbone master of the design, connected to the i.MX of APF27
-      </brief>
-      <detailed>
-       This block is the wishbone master of the design, connected to the i.MX of APF27
-      </detailed>     
     </description>    
   </informations>
 
   <parameters>
+    <parameter name="imx_clk" type="real" value="133" context="user"/>
   </parameters>
 
   <interfaces>
@@ -23,10 +19,11 @@
       <input name="clk" type="boolean" width="1" purpose="clock" />
       <input name="rst" type="boolean" width="1" purpose="reset" />
       
-      <input name="imx_addr" type="expression" width="$wb_addr_width" />
-      <input name="imx_cs_n" type="boolean" width="1" />
-      <input name="imx_oe_n" type="boolean" width="1" />
-      <input name="imx_eb3_n" type="boolean" width="1" />
+      <input name="imx_addr" type="expression" width="$wb_addr_width" clock="$imx_clk" />
+      <input name="imx_data" type="expression" width="$wb_data_width" clock="$imx_clk" />      
+      <input name="imx_cs_n" type="boolean" width="1" clock="$imx_clk" />
+      <input name="imx_oe_n" type="boolean" width="1" clock="$imx_clk"/>
+      <input name="imx_eb3_n" type="boolean" width="1" clock="$imx_clk"/>
       
       <input name="ack_i" type="boolean" width="1" purpose="wb" />
       <input name="dat_i" width="$wb_data_width" purpose="wb" />