finished VHDL gen. (but have to test further

[blast.git] / reference.xsd

diff --git a/reference.xsd b/reference.xsd
index b219bfaf9aace74b4fee2c01b121388e691ccc6e..29f5d2821f7270e09ee8af42cd7b74732fe4c173 100644 (file)
--- a/reference.xsd
+++ b/reference.xsd
@@ -19,6 +19,7 @@
        <xs:attribute name="type" type="typeiface"/>
        <xs:attribute ref="purpose"/>
        <xs:attribute ref="multiplicity"/>
+       <xs:attribute name="endian" type="typeendian" use="optional"/>  
     </xs:attributeGroup>
 
 
@@ -47,6 +48,13 @@
        <xs:enumeration value="natural"/>
       </xs:restriction>
     </xs:simpleType>
+    
+    <xs:simpleType name="typeendian">
+      <xs:restriction base="xs:string">
+       <xs:enumeration value="little"/>
+       <xs:enumeration value="big"/>
+      </xs:restriction>
+    </xs:simpleType>
       
     <xs:attribute name="wishbone" type="xs:string"/>
     <xs:attribute name="context" type="xs:string" />
@@ -207,9 +215,10 @@
     <!-- Racine du document -->
 
     <xs:element name="block">
-       <xs:complexType>
-           <xs:group ref="blockElmtGroup"/>
-       </xs:complexType>
+      <xs:complexType>
+       <xs:group ref="blockElmtGroup"/>
+       <xs:attribute name="version" type="xs:string" use="optional" />
+      </xs:complexType>
     </xs:element>
 
 </xs:schema>