}\r
\r
bool BlockImplementation::checkPatterns() {\r
- if (reference == NULL) return false;\r
+\r
+\r
+ if (reference == NULL) {\r
+ cout << "no ref. while checking patterns of implementation " << endl;\r
+ return false;\r
+ }\r
\r
AbstractInterface* iface; \r
QHashIterator<QString,QString> iterI(consumptionPattern);\r
while (iterI.hasNext()) {\r
iterI.next();\r
iface = reference->getIfaceFromName(iterI.key());\r
- if (iface == NULL) return false;\r
+ if (iface == NULL) {\r
+ cout << "cannot found an input ref. iface for impl. iface " << qPrintable(iterI.key()) << endl;\r
+ return false;\r
+ }\r
}\r
QHashIterator<QString,QString> iterO(productionPattern);\r
while (iterO.hasNext()) {\r
iterO.next();\r
iface = reference->getIfaceFromName(iterO.key());\r
- if (iface == NULL) return false;\r
+ if (iface == NULL) {\r
+ cout << "cannot found an output ref. iface for impl. iface " << qPrintable(iterI.key()) << endl;\r
+ return false;\r
+ }\r
} \r
return true; \r
}\r
if (reference->isWBConfigurable()) {\r
genController = true;\r
controllerFile = path;\r
+ controllerFile += "/";\r
controllerFile.append(block->getName());\r
controllerFile.append("_ctrl.vhd"); \r
}\r
controllerFile = "nofile.vhd"; \r
}\r
coreFile = path;\r
+ coreFile += "/";\r
coreFile.append(block->getName());\r
coreFile.append(".vhd");\r
\r
for(int i = 0; i < 50; i++) {\r
out << "--";\r
}\r
- out << "\n--\n";\r
+ out << "\n--" << endl;\r
QString fileName = coreFile;\r
- out << "-- File : " << fileName << "\n";\r
- out << "--\n";\r
+ out << "-- File : " << fileName << endl;\r
+ out << "--" << endl;\r
QDomElement eltAuthor = elt.firstChildElement("author");\r
QString firstName = eltAuthor.attribute("firstname","");\r
QString lastName = eltAuthor.attribute("lastname","");\r
QString mail = eltAuthor.attribute("mail","");\r
- out << "-- Author(s) : "<<firstName+" "<<lastName<<" ("<<mail<<")\n";\r
- out << "--\n";\r
+ out << "-- Author(s) : "<<firstName+" "<<lastName<<" ("<<mail<<")" << endl;\r
+ out << "--" << endl;\r
QDomElement eltDate = eltAuthor.nextSiblingElement("date");\r
QString crea = eltDate.attribute("creation","");\r
- out << "-- Creation Date : "<<crea<<"\n";\r
- out << "--\n";\r
+ out << "-- Creation Date : "<<crea<< endl;\r
+ out << "--" << endl;\r
QDomElement eltRelated = eltDate.nextSiblingElement("related_files");\r
QString relateds = eltRelated.attribute("list","");\r
- out << "-- Related files :\n"<<relateds<<"\n";\r
- out << "--\n";\r
+ out << "-- Related files :\n"<<relateds<<endl;\r
+ out << "--" << endl;\r
QDomElement eltDesc = eltRelated.nextSiblingElement("description");\r
QDomElement desc = eltDesc.firstChildElement();\r
QString descTxt = desc.text();\r
- out << "-- Decription :\n"<<descTxt<<"\n";\r
- out << "--\n";\r
+ out << "-- Decription :\n"<<descTxt<<endl;\r
+ out << "--" << endl;\r
QDomElement eltNote = eltDesc.nextSiblingElement("description");\r
QDomElement note = eltNote.firstChildElement();\r
QString noteTxt = note.text();\r
- out << "-- Note :\n"<<noteTxt<<"\n";\r
- out << "--\n";\r
+ out << "-- Note :\n"<<noteTxt<<endl;\r
+ out << "--" << endl;\r
for(int i = 0; i < 50; i++) {\r
out << "--";\r
}\r
- out << "\n\n";\r
+ out << endl << endl;\r
}\r
\r
// This function generates the library part of the VHDL document\r
for(int i = 0; i < listLib.length(); i++) {\r
QDomNode nodeLib = listLib.item(i);\r
QDomElement eltLib = nodeLib.toElement();\r
- QString nameLib = eltLib.attribute("name", "");\r
- out << "library " << nameLib << ";\n";\r
+ QString nameLib = eltLib.attribute("name","none");\r
+ out << "library " << nameLib << ";" << endl;\r
QDomNodeList listPack = eltLib.elementsByTagName("package");\r
for(int j = 0; j < listPack.length(); j++) {\r
QDomNode nodePack = listPack.item(j);\r
QDomElement eltPack = nodePack.toElement();\r
- QString namePack = eltPack.attribute("name", "");\r
- QString usePack = elt.attribute("use","");\r
- out << "use " << nameLib << "." << namePack << "." << usePack << ";\n";\r
+ QString namePack = eltPack.attribute("name","none");\r
+ QString usePack = eltPack.attribute("use","none");\r
+ out << "use " << nameLib << "." << namePack << "." << usePack << endl;\r
}\r
- out << "\n";\r
+ out << endl;\r
}\r
}\r
\r
void BlockImplementation::generateEntity(QTextStream& out, bool hasController) throw(Exception) {\r
\r
int i=0;\r
- nameEnt = reference->getName();\r
+ nameEnt = block->getName();\r
//QList<BlockParameter*> listParams = reference->getParameters();\r
- QList<AbstractInterface*> listInputs = reference->getInputs();\r
- QList<AbstractInterface*> listOutputs = reference->getOutputs();\r
- QList<AbstractInterface*> listBidirs = reference->getBidirs();\r
+ QList<AbstractInterface*> listInputs = block->getInputs();\r
+ QList<AbstractInterface*> listOutputs = block->getOutputs();\r
+ QList<AbstractInterface*> listBidirs = block->getBidirs();\r
QString typePort, namePort;\r
\r
- out << "entity " << nameEnt << " is\n";\r
+ out << "entity " << nameEnt << " is" << endl;\r
\r
\r
/* TODO : rewrite the generation to take into acocunt the new object hierarchy */\r
\r
// Generation of the generics\r
- QList<BlockParameter*> listGenerics = reference->getGenericParameters();\r
+ QList<BlockParameter*> listGenerics = block->getGenericParameters();\r
if ((!listGenerics.isEmpty()) || (hasController)) {\r
out << " generic (" << endl;\r
if (hasController) {\r
out << endl;\r
}\r
for(i=0;i<listGenerics.size()-1;i++) {\r
- out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0);\r
+ out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
}\r
- out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma);\r
+ out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
\r
out << " );" << endl;\r
}\r
\r
// Generation of the clk & rst signals\r
out << " -- clk/rst" << endl;\r
- for(int i = 0; i < listInputs.size(); i++) {\r
- if(listInputs.at(i)->getPurpose() == AbstractInterface::Clock || listInputs.at(i)->getPurpose() == AbstractInterface::Reset) {\r
- out << " " << listInputs.at(i)->getName() << " : in std_logic;" << endl;\r
+ foreach(AbstractInterface* iface, listInputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
+ out << " " << iface->getName() << " : in std_logic;" << endl;\r
}\r
}\r
\r
out << " -- registers r/w via wishbone" << endl;\r
QList<BlockParameter*> listWB = reference->getWishboneParameters();\r
for(i=0;i<listWB.size()-1;i++) {\r
- out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0);\r
+ out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
}\r
- out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma);\r
+ out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
}\r
\r
\r
- // Generation of the data signals\r
- out << "-- data ports\n";\r
- for(int i = 0; i < listInputs.size(); i++) {\r
- namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listInputs.at(i)->getName()));\r
- if(listInputs.at(i)->getWidth().compare("1"))\r
- typePort = "std_logic";\r
- else\r
- typePort = calculateWidth(listInputs.at(i)->getWidth());\r
- if(listInputs.at(i)->getPurpose() == 1)\r
- out << namePort << " : in std_logic_vector(" << typePort << " -1 downto 0) ;\n";\r
+ int count = 0;\r
+ foreach(AbstractInterface* iface, block->getInterfaces()) {\r
+ if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++;\r
}\r
+ // Generation of the data/control signals\r
\r
- for(int i = 0; i < listOutputs.size(); i++) {\r
- namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listOutputs.at(i)->getName()));\r
- if(listOutputs.at(i)->getWidth().compare("1"))\r
- typePort = "std_logic";\r
- else\r
- typePort = calculateWidth(listOutputs.at(i)->getWidth());\r
- if(listOutputs.at(i)->getPurpose() == 1)\r
- out << namePort << " : out std_logic_vector(" << typePort << " -1 downto 0) ;\n";\r
- }\r
+ int flag = 0;\r
+ bool first = true;\r
\r
- for(int i = 0; i < listBidirs.size(); i++) {\r
- namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listBidirs.at(i)->getName()));\r
- if(listBidirs.at(i)->getWidth().compare(("1")))\r
- typePort = "std_logic";\r
- else\r
- typePort = calculateWidth((listBidirs.at(i)->getWidth()));\r
- if(listBidirs.at(i)->getPurpose() == 1)\r
- out << namePort << " : inout std_logic_vector(" << typePort << " -1 downto 0) ;\n";\r
+ foreach(AbstractInterface* iface, listInputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Data) {\r
+ if (first) {\r
+ out << " -- input data ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listInputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Control) {\r
+ if (first) {\r
+ out << " -- input control ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listOutputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Data) {\r
+ if (first) {\r
+ out << " -- output data ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listOutputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Control) {\r
+ if (first) {\r
+ out << " -- output control ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listBidirs) {\r
+ if(iface->getPurpose() == AbstractInterface::Data) {\r
+ if (first) {\r
+ out << " -- bidirs data ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
}\r
+ out << " );" << endl << endl;\r
+ out << "end " << nameEnt << ";" << endl << endl;\r
}\r
\r
// This function generates the architecture part of the VHDL document\r
void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& out) throw(Exception) {\r
\r
QString expr;\r
- QDomElement eltArch = elt.nextSiblingElement("architecture");\r
- out << "architecture " << nameEnt <<"_1 of " << nameEnt << "is\n";\r
- QString implText = eltArch.text();\r
- QStringList listLine = implText.split("\n");\r
+ QString code = elt.text();\r
+ cout << qPrintable(code) << endl;\r
+ out << "architecture rtl of " << nameEnt << " is" << endl;\r
+\r
+ QStringList listLine = code.split("\n");\r
for(int i =0; i < listLine.size(); i++) {\r
- if(listLine.at(i).contains(QRegularExpression("@foreach{")) != -1) {\r
+ QString line = listLine.at(i).simplified();\r
+\r
+ /*\r
+ if(listLine.at(i).contains(QRegularExpression("@foreach{"))) {\r
while(listLine.at(i).compare("@endforeach") != -1) {\r
expr = expr + listLine.at(i) + '\n';\r
i++;\r
expr = expr + listLine.at(i);\r
out << evalComplex(expr, 1) << '\n';\r
}\r
- if(listLine.at(i).contains(QRegularExpression("@caseeach{")) != -1) {\r
+ if(listLine.at(i).contains(QRegularExpression("@caseeach{"))) {\r
while(listLine.at(i).compare("@endcaseeach") != -1) {\r
expr = expr + listLine.at(i) + '\n';\r
i++;\r
expr = expr + listLine.at(i);\r
out << evalComplex(expr, 2) << '\n';\r
}\r
-\r
- if(listLine.at(i).contains('@') == -1)\r
- out << listLine.at(i) << "\n";\r
- else\r
- out << eval(listLine.at(i), out) << "\n";\r
+*/\r
+ if(line.contains("@{")) {\r
+ out << line << endl;\r
+ }\r
}\r
}\r
\r
