+ //QList<BlockParameter*> listParams = reference->getParameters();\r
+ QList<AbstractInterface*> listInputs = getInputs();\r
+ QList<AbstractInterface*> listOutputs = getOutputs();\r
+ QList<AbstractInterface*> listBidirs = getBidirs(); \r
+\r
+ // Generation of the generics\r
+ QList<BlockParameter*> listGenerics = getGenericParameters();\r
+ if ((!listGenerics.isEmpty()) || (hasController)) {\r
+ out << indent << " generic (" << endl;\r
+ if (hasController) {\r
+ out << indent << " wb_data_width : integer = 16;" << endl;\r
+ out << indent << " wb_addr_width : integer = 12";\r
+ if (!listGenerics.isEmpty()) out << indent << ";";\r
+ out << endl;\r
+ }\r
+ for(i=0;i<listGenerics.size()-1;i++) {\r
+ out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
+ }\r
+ out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
+\r
+ out << indent << " );" << endl;\r
+ }\r
+\r
+ out << indent << " port (" << endl;\r
+\r
+ QString ports = "";\r
+ QTextStream outPorts(&ports);\r
+\r
+ // Generation of the clk & rst signals\r
+ outPorts << indent << " -- clk/rst" << endl;\r
+ foreach(AbstractInterface* iface, listInputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
+ outPorts << indent << " " << iface->getName() << " : in std_logic;" << endl;\r
+ }\r
+ }\r
+ foreach(AbstractInterface* iface, listOutputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
+ outPorts << indent << " " << iface->getName() << " : out std_logic;" << endl;\r
+ }\r
+ }\r
+\r
+ if (hasController) {\r
+ // Generation of the wishbone signals\r
+ outPorts << indent << " -- registers r/w via wishbone" << endl;\r
+ QList<BlockParameter*> listWB = reference->getWishboneParameters();\r
+ for(i=0;i<listWB.size()-1;i++) {\r
+ outPorts << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
+ }\r
+ outPorts << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
+ }\r
+\r
+ // Generation of the data/control signals\r
+\r
+ QList<AbstractInterface*> listIface = getInterfaces(AbstractInterface::Input, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- input data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
+ }\r
+ }\r
+ listIface = getInterfaces(AbstractInterface::Input, AbstractInterface::Control);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- input control ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
+ }\r
+ }\r
+ listIface = getInterfaces(AbstractInterface::Output, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- output data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
+ }\r
+ }\r
+ listIface = getInterfaces(AbstractInterface::Output, AbstractInterface::Control);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- output control ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
+ }\r
+ }\r
+ listIface = getInterfaces(AbstractInterface::InOut, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- bidirs data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
+ }\r
+ }\r
+\r
+ ports.chop(2);\r
+ ports += "\n";\r
+ out << ports;\r
+ out << indent << " );" << endl << endl;\r
+\r
+}\r
+\r
+void FunctionalBlock::generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception) {\r
+ QRegularExpression rxPort("@\\{([a-zA-Z0-9_]+)\\}");\r
+ QString expr;\r
+ QString code = elt.text();\r
+ //cout << qPrintable(code) << endl;\r
+ out << "architecture rtl of " << name << " is" << endl;\r
+\r
+ QStringList listLine = code.split("\n");\r
+ for(int i =0; i < listLine.size(); i++) {\r
+ QString line = listLine.at(i).simplified();\r
+\r
+ /*\r
+ if(listLine.at(i).contains(QRegularExpression("@foreach{"))) {\r
+ while(listLine.at(i).compare("@endforeach") != -1) {\r
+ expr = expr + listLine.at(i) + '\n';\r
+ i++;\r
+ }\r
+ expr = expr + listLine.at(i);\r
+ out << evalComplex(expr, 1) << '\n';\r
+ }\r
+ if(listLine.at(i).contains(QRegularExpression("@caseeach{"))) {\r
+ while(listLine.at(i).compare("@endcaseeach") != -1) {\r
+ expr = expr + listLine.at(i) + '\n';\r
+ i++;\r
+ }\r
+ expr = expr + listLine.at(i);\r
+ out << evalComplex(expr, 2) << '\n';\r
+ }\r
+*/\r
+ if(line.contains("@{")) {\r
+ QMap<QString,QString> modifs;\r
+ //cout << qPrintable(line) << endl;\r
+ QRegularExpressionMatchIterator matchPort = rxPort.globalMatch(line);\r
+ while(matchPort.hasNext()) {\r
+ QRegularExpressionMatch m = matchPort.next();\r
+ QString refName = m.captured(1);\r
+ AbstractInterface* refIface = reference->getIfaceFromName(refName);\r
+ QString funName = getIfaceUserName(refIface);\r
+ if (!funName.isEmpty()) {\r
+ modifs.insert(m.captured(0),funName);\r
+ //cout << "replace " << qPrintable(refIface->getName()) << " by " << qPrintable(funIface->getName()) << endl;\r
+ }\r
+ }\r
+ QMapIterator<QString,QString> iterM(modifs);\r
+ while(iterM.hasNext()) {\r
+ iterM.next();\r
+ QString oldName = iterM.key();\r
+ QString newName = iterM.value();\r
+ line.replace(oldName,newName);\r
+ }\r
+ }\r
+ out << line << endl;\r
+ }\r
+\r
+ out << "end rtl;" << endl;\r
+}\r
+\r
+void FunctionalBlock::generateController(QTextStream &out) throw(Exception) {\r
