finished VHDL gen. (but have to test further

[blast.git] / VHDLConverter.cpp

diff --git a/VHDLConverter.cpp b/VHDLConverter.cpp
index d3938b29e453c4fca1f19ec7a22b9c07af1a8760..88b371f01440213679c51c2b42927ba2486a97c5 100644 (file)
--- a/VHDLConverter.cpp
+++ b/VHDLConverter.cpp
@@ -459,12 +459,12 @@ void VHDLConverter::loadVHDLFile() {
     else {\r
       widthStr = "std_logic_vector(";\r
       if (iface->getEndianess() == AbstractInterface::LittleEndian) {\r
     else {\r
       widthStr = "std_logic_vector(";\r
       if (iface->getEndianess() == AbstractInterface::LittleEndian) {\r

-        widthStr += iface->getWidth();\r
+        widthStr += iface->getWidthString();\r

         widthStr += " downto 0)";\r
       }\r
       else {\r
         widthStr += "0 to ";\r
         widthStr += " downto 0)";\r
       }\r
       else {\r
         widthStr += "0 to ";\r

-        widthStr += iface->getWidth();\r
+        widthStr += iface->getWidthString();\r

         widthStr += ")";\r
       }\r
     }\r
         widthStr += ")";\r
       }\r
     }\r


@@ -651,7 +651,7 @@ void VHDLConverter::generateRefXml(QDomDocument& doc) {
         QDomElement input = doc.createElement("input");\r
         input.setAttribute("name",iface->getName());\r
         input.setAttribute("type",iface->getTypeString());\r
         QDomElement input = doc.createElement("input");\r
         input.setAttribute("name",iface->getName());\r
         input.setAttribute("type",iface->getTypeString());\r

-        input.setAttribute("width",iface->getWidth());\r
+        input.setAttribute("width",iface->getWidthString());\r

         input.setAttribute("multiplicity","1");\r
         input.setAttribute("purpose",iface->getPurposeString());\r
         input.setAttribute("endian",iface->getEndianessString());\r
         input.setAttribute("multiplicity","1");\r
         input.setAttribute("purpose",iface->getPurposeString());\r
         input.setAttribute("endian",iface->getEndianessString());\r


@@ -673,7 +673,7 @@ void VHDLConverter::generateRefXml(QDomDocument& doc) {
         QDomElement output = doc.createElement("output");\r
         output.setAttribute("name",iface->getName());\r
         output.setAttribute("type",iface->getTypeString());\r
         QDomElement output = doc.createElement("output");\r
         output.setAttribute("name",iface->getName());\r
         output.setAttribute("type",iface->getTypeString());\r

-        output.setAttribute("width",iface->getWidth());\r
+        output.setAttribute("width",iface->getWidthString());\r

         output.setAttribute("multiplicity","1");\r
         output.setAttribute("purpose",iface->getPurposeString());\r
         output.setAttribute("endian",iface->getEndianessString());\r
         output.setAttribute("multiplicity","1");\r
         output.setAttribute("purpose",iface->getPurposeString());\r
         output.setAttribute("endian",iface->getEndianessString());\r


@@ -695,7 +695,7 @@ void VHDLConverter::generateRefXml(QDomDocument& doc) {
         QDomElement bidir = doc.createElement("bidir");\r
         bidir.setAttribute("name",iface->getName());\r
         bidir.setAttribute("type",iface->getTypeString());\r
         QDomElement bidir = doc.createElement("bidir");\r
         bidir.setAttribute("name",iface->getName());\r
         bidir.setAttribute("type",iface->getTypeString());\r

-        bidir.setAttribute("width",iface->getWidth());\r
+        bidir.setAttribute("width",iface->getWidthString());\r

         bidir.setAttribute("multiplicity","1");\r
         bidir.setAttribute("purpose",iface->getPurposeString());\r
         bidir.setAttribute("endian",iface->getEndianessString());\r
         bidir.setAttribute("multiplicity","1");\r
         bidir.setAttribute("purpose",iface->getPurposeString());\r
         bidir.setAttribute("endian",iface->getEndianessString());\r