return true; \r
}\r
\r
-void BlockImplementation::generateVHDL(FunctionalBlock* _block, const QString &path) throw(Exception) {\r
-\r
- block = _block;\r
-\r
- QFile implFile(xmlFile);\r
-\r
- // reading in into QDomDocument\r
- QDomDocument document("implFile");\r
-\r
- if (!implFile.open(QIODevice::ReadOnly)) {\r
- throw(Exception(IMPLFILE_NOACCESS));\r
- }\r
- if (!document.setContent(&implFile)) {\r
- implFile.close();\r
- throw(Exception(IMPLFILE_NOACCESS));\r
- }\r
- implFile.close();\r
-\r
- bool genController = false;\r
- QString coreFile = "";\r
- QString controllerFile = "";\r
-\r
- if (reference->isWBConfigurable()) {\r
- genController = true;\r
- controllerFile = path;\r
- controllerFile.append(block->getName());\r
- controllerFile.append("_ctrl.vhd"); \r
- }\r
- else {\r
- controllerFile = "nofile.vhd"; \r
- }\r
- coreFile = path;\r
- coreFile.append(block->getName());\r
- coreFile.append(".vhd");\r
-\r
- QFile vhdlCore(coreFile);\r
- QFile vhdlController(controllerFile);\r
-\r
- if (!vhdlCore.open(QIODevice::WriteOnly)) {\r
- throw(Exception(VHDLFILE_NOACCESS));\r
- }\r
-\r
- if (genController) {\r
- if (!vhdlController.open(QIODevice::WriteOnly)) {\r
- throw(Exception(VHDLFILE_NOACCESS));\r
- }\r
- }\r
- QTextStream outCore(&vhdlCore);\r
- QTextStream outController;\r
- if (genController) {\r
- outController.setDevice(&vhdlController);\r
- }\r
-\r
- try {\r
-\r
-\r
- //Get the root element\r
- QDomElement impl = document.documentElement();\r
- QDomElement eltComments = impl.firstChildElement("comments");\r
- generateComments(eltComments, coreFile, outCore);\r
- QDomElement eltLibs = eltComments.nextSiblingElement("libraries");\r
- generateLibraries(eltLibs, outCore);\r
- generateEntity(outCore, genController);\r
- QDomElement eltArch = eltLibs.nextSiblingElement("architecture");\r
- generateArchitecture(eltArch, outCore);\r
- if (genController) {\r
- generateController(outController);\r
- }\r
- }\r
- catch(Exception err) {\r
- throw(err);\r
- }\r
-\r
- vhdlCore.close();\r
- vhdlController.close();\r
-}\r
-\r
-// This function generates the comments part of the VHDL document\r
-void BlockImplementation::generateComments(QDomElement &elt, QString coreFile, QTextStream& out) throw(Exception) {\r
-\r
- for(int i = 0; i < 50; i++) {\r
- out << "--";\r
- }\r
- out << "\n--\n";\r
- QString fileName = coreFile;\r
- out << "-- File : " << fileName << "\n";\r
- out << "--\n";\r
- QDomElement eltAuthor = elt.firstChildElement("author");\r
- QString firstName = eltAuthor.attribute("firstname","");\r
- QString lastName = eltAuthor.attribute("lastname","");\r
- QString mail = eltAuthor.attribute("mail","");\r
- out << "-- Author(s) : "<<firstName+" "<<lastName<<" ("<<mail<<")\n";\r
- out << "--\n";\r
- QDomElement eltDate = eltAuthor.nextSiblingElement("date");\r
- QString crea = eltDate.attribute("creation","");\r
- out << "-- Creation Date : "<<crea<<"\n";\r
- out << "--\n";\r
- QDomElement eltRelated = eltDate.nextSiblingElement("related_files");\r
- QString relateds = eltRelated.attribute("list","");\r
- out << "-- Related files :\n"<<relateds<<"\n";\r
- out << "--\n";\r
- QDomElement eltDesc = eltRelated.nextSiblingElement("description");\r
- QDomElement desc = eltDesc.firstChildElement();\r
- QString descTxt = desc.text();\r
- out << "-- Decription :\n"<<descTxt<<"\n";\r
- out << "--\n";\r
- QDomElement eltNote = eltDesc.nextSiblingElement("description");\r
- QDomElement note = eltNote.firstChildElement();\r
- QString noteTxt = note.text();\r
- out << "-- Note :\n"<<noteTxt<<"\n";\r
- out << "--\n";\r
- for(int i = 0; i < 50; i++) {\r
- out << "--";\r
- }\r
- out << "\n\n";\r
-}\r
-\r
-// This function generates the library part of the VHDL document\r
-void BlockImplementation::generateLibraries(QDomElement &elt, QTextStream& out) throw(Exception) {\r
-\r
- QDomNodeList listLib = elt.elementsByTagName("library");\r
- for(int i = 0; i < listLib.length(); i++) {\r
- QDomNode nodeLib = listLib.item(i);\r
- QDomElement eltLib = nodeLib.toElement();\r
- QString nameLib = eltLib.attribute("name","none");\r
- out << "library " << nameLib << ";\n";\r
- QDomNodeList listPack = eltLib.elementsByTagName("package");\r
- for(int j = 0; j < listPack.length(); j++) {\r
- QDomNode nodePack = listPack.item(j);\r
- QDomElement eltPack = nodePack.toElement();\r
- QString namePack = eltPack.attribute("name","none");\r
- QString usePack = eltPack.attribute("use","none");\r
- out << "use " << nameLib << "." << namePack << "." << usePack << endl;\r
- }\r
- out << endl;\r
- }\r
-}\r
-\r
-// This function generates the entity part of the VHDL document\r
-void BlockImplementation::generateEntity(QTextStream& out, bool hasController) throw(Exception) {\r
-\r
- int i=0;\r
- nameEnt = block->getName();\r
- //QList<BlockParameter*> listParams = reference->getParameters();\r
- QList<AbstractInterface*> listInputs = block->getInputs();\r
- QList<AbstractInterface*> listOutputs = block->getOutputs();\r
- QList<AbstractInterface*> listBidirs = block->getBidirs();\r
- QString typePort, namePort;\r
-\r
- out << "entity " << nameEnt << " is\n";\r
-\r
-\r
- /* TODO : rewrite the generation to take into acocunt the new object hierarchy */\r
-\r
- // Generation of the generics\r
- QList<BlockParameter*> listGenerics = block->getGenericParameters();\r
- if ((!listGenerics.isEmpty()) || (hasController)) {\r
- out << " generic (" << endl;\r
- if (hasController) {\r
- out << " wb_data_width : integer = 16;" << endl;\r
- out << " wb_addr_width : integer = 12";\r
- if (!listGenerics.isEmpty()) out << ";";\r
- out << endl;\r
- }\r
- for(i=0;i<listGenerics.size()-1;i++) {\r
- out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
- }\r
- out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
-\r
- out << " );" << endl;\r
- }\r
-\r
- out << " port (" << endl;\r
-\r
- // Generation of the clk & rst signals\r
- out << " -- clk/rst" << endl;\r
- foreach(AbstractInterface* iface, listInputs) {\r
- if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
- out << " " << iface->getName() << " : in std_logic;" << endl;\r
- }\r
- }\r
-\r
- if (hasController) {\r
- // Generation of the wishbone signals\r
- out << " -- registers r/w via wishbone" << endl;\r
- QList<BlockParameter*> listWB = reference->getWishboneParameters();\r
- for(i=0;i<listWB.size()-1;i++) {\r
- out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
- }\r
- out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
- }\r
-\r
-\r
- int count = 0;\r
- foreach(AbstractInterface* iface, block->getInterfaces()) {\r
- if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++;\r
- }\r
- // Generation of the data/control signals\r
-\r
- int flag = 0;\r
- bool first = true;\r
-\r
- foreach(AbstractInterface* iface, listInputs) {\r
- if(iface->getPurpose() == AbstractInterface::Data) {\r
- if (first) {\r
- out << " -- input data ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
- }\r
- }\r
- first = true;\r
- foreach(AbstractInterface* iface, listInputs) {\r
- if(iface->getPurpose() == AbstractInterface::Control) {\r
- if (first) {\r
- out << " -- input control ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
- }\r
- }\r
- first = true;\r
- foreach(AbstractInterface* iface, listOutputs) {\r
- if(iface->getPurpose() == AbstractInterface::Data) {\r
- if (first) {\r
- out << " -- output data ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
- }\r
- }\r
- first = true;\r
- foreach(AbstractInterface* iface, listOutputs) {\r
- if(iface->getPurpose() == AbstractInterface::Control) {\r
- if (first) {\r
- out << " -- output control ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
- }\r
- }\r
- first = true;\r
- foreach(AbstractInterface* iface, listBidirs) {\r
- if(iface->getPurpose() == AbstractInterface::Data) {\r
- if (first) {\r
- out << " -- bidirs data ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
- }\r
- }\r
- out << " );" << endl << endl;\r
- out << "end " << nameEnt << ";" << endl << endl;\r
-}\r
-\r
-// This function generates the architecture part of the VHDL document\r
-void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& out) throw(Exception) {\r
-\r
- QString expr;\r
- QString code = elt.text();\r
- cout << qPrintable(code) << endl;\r
- out << "architecture rtl of " << nameEnt << " is" << endl;\r
-\r
- QStringList listLine = code.split("\n");\r
- for(int i =0; i < listLine.size(); i++) {\r
- QString line = listLine.at(i).simplified();\r
-\r
- /*\r
- if(listLine.at(i).contains(QRegularExpression("@foreach{"))) {\r
- while(listLine.at(i).compare("@endforeach") != -1) {\r
- expr = expr + listLine.at(i) + '\n';\r
- i++;\r
- }\r
- expr = expr + listLine.at(i);\r
- out << evalComplex(expr, 1) << '\n';\r
- }\r
- if(listLine.at(i).contains(QRegularExpression("@caseeach{"))) {\r
- while(listLine.at(i).compare("@endcaseeach") != -1) {\r
- expr = expr + listLine.at(i) + '\n';\r
- i++;\r
- }\r
- expr = expr + listLine.at(i);\r
- out << evalComplex(expr, 2) << '\n';\r
- }\r
-*/\r
- if(line.contains("@{")) {\r
- out << line << endl;\r
- }\r
- }\r
-}\r
-\r
-void BlockImplementation::generateController(QTextStream &out) throw(Exception) {\r
-}\r
-\r
QString BlockImplementation::eval(QString line, QTextStream& out) {\r
QString res, s, begLine, endLine, expr;\r
evaluator->setExpression(line);\r
