moved vhdl gen. into block

[blast.git] / lib / implementations / rgb3sx8_to_ycbcr_3DSP_impl.xml

diff --git a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
index 3db4b59982937de98dc43deaf691c33e378bcdeb..e186114e0ab6008e76f6880177b1c1dab1cef349 100644 (file)
--- a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
+++ b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
@@ -304,8 +304,6 @@ std_logic_vector(cb_dly1(7 downto 0)) when do_out_cb = '1' else
 std_logic_vector(cr(7 downto 0)) when do_out_cr = '1' else
 (others => '0');
 @{ycbcr_out_enb} <= do_out_y or do_out_cb or do_out_cr;
-
-end rtl;
 </architecture>
   <patterns>
     <delta value="3"/>