started VHDL generation of GroupBlock

[blast.git] / lib / implementations / rgb3sx8_to_ycbcr_3DSP_impl.xml

diff --git a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
index 3db4b59982937de98dc43deaf691c33e378bcdeb..e9415791a2448b527085f8b89fe09401f9a352d2 100644 (file)
--- a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
+++ b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
@@ -13,7 +13,7 @@
       <package name="numeric_std" use="all"/>
     </library>
   </libraries>
       <package name="numeric_std" use="all"/>
     </library>
   </libraries>

-  <architecture>
+  <architecture comp_list="mult_accum">

 component mult_accum
 port (
 @{clk} : in std_logic;
 component mult_accum
 port (
 @{clk} : in std_logic;


@@ -304,8 +304,6 @@ std_logic_vector(cb_dly1(7 downto 0)) when do_out_cb = '1' else
 std_logic_vector(cr(7 downto 0)) when do_out_cr = '1' else
 (others => '0');
 @{ycbcr_out_enb} &lt;= do_out_y or do_out_cb or do_out_cr;
 std_logic_vector(cr(7 downto 0)) when do_out_cr = '1' else
 (others => '0');
 @{ycbcr_out_enb} &lt;= do_out_y or do_out_cb or do_out_cr;

-
-end rtl;

 </architecture>
   <patterns>
     <delta value="3"/>
 </architecture>
   <patterns>
     <delta value="3"/>