started VHDL generation of GroupBlock

[blast.git] / lib / references / rgb3sx8_to_ycbcr_3DSP.xml

diff --git a/lib/references/rgb3sx8_to_ycbcr_3DSP.xml b/lib/references/rgb3sx8_to_ycbcr_3DSP.xml
index 5bbc8566b197bd03318bbd8366c23aee74c50d65..17d1870510da65fddd3568f09b489cbb73497b19 100644 (file)
--- a/lib/references/rgb3sx8_to_ycbcr_3DSP.xml
+++ b/lib/references/rgb3sx8_to_ycbcr_3DSP.xml
@@ -13,11 +13,11 @@
     <inputs>
       <input endian="little" type="boolean" purpose="clock" multiplicity="1" width="1" name="clk"/>
       <input endian="little" type="boolean" purpose="reset" multiplicity="1" width="1" name="reset"/>
     <inputs>
       <input endian="little" type="boolean" purpose="clock" multiplicity="1" width="1" name="clk"/>
       <input endian="little" type="boolean" purpose="reset" multiplicity="1" width="1" name="reset"/>

-      <input endian="little" type="natural" purpose="data" multiplicity="1" width="7" name="rgb_in"/>
+      <input endian="little" type="natural" purpose="data" multiplicity="1" width="8" name="rgb_in"/>

       <control iface="rgb_in"/>
     </inputs>
     <outputs>
       <control iface="rgb_in"/>
     </inputs>
     <outputs>

-      <output endian="little" type="natural" purpose="data" multiplicity="1" width="7" name="ycbcr_out"/>
+      <output endian="little" type="natural" purpose="data" multiplicity="1" width="8" name="ycbcr_out"/>

       <control iface="ycbcr_out"/>
     </outputs>
   </interfaces>
       <control iface="ycbcr_out"/>
     </outputs>
   </interfaces>