+\r
+\r
+void FunctionalBlock::generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController) throw(Exception) {\r
+\r
+ int i=0;\r
+ QString indent = "";\r
+ for(i=0;i<indentLevel;i++) {\r
+ indent += " ";\r
+ }\r
+ \r
+ //QList<BlockParameter*> listParams = reference->getParameters();\r
+ QList<AbstractInterface*> listInputs = getInputs();\r
+ QList<AbstractInterface*> listOutputs = getOutputs();\r
+ QList<AbstractInterface*> listBidirs = getBidirs(); \r
+\r
+ // Generation of the generics\r
+ QList<BlockParameter*> listGenerics = getGenericParameters();\r
+ if ((!listGenerics.isEmpty()) || (hasController)) {\r
+ out << indent << " generic (" << endl;\r
+ if (hasController) {\r
+ out << indent << " wb_data_width : integer = 16;" << endl;\r
+ out << indent << " wb_addr_width : integer = 12";\r
+ if (!listGenerics.isEmpty()) out << indent << ";";\r
+ out << endl;\r
+ }\r
+ for(i=0;i<listGenerics.size()-1;i++) {\r
+ out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
+ }\r
+ out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
+\r
+ out << indent << " );" << endl;\r
+ }\r
+\r
+ out << indent << " port (" << endl;\r
+\r
+ // Generation of the clk & rst signals\r
+ out << indent << " -- clk/rst" << endl;\r
+ foreach(AbstractInterface* iface, listInputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
+ out << indent << " " << iface->getName() << " : in std_logic;" << endl;\r
+ }\r
+ }\r
+ foreach(AbstractInterface* iface, listOutputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
+ out << indent << " " << iface->getName() << " : out std_logic;" << endl;\r
+ }\r
+ }\r
+\r
+ if (hasController) {\r
+ // Generation of the wishbone signals\r
+ out << indent << " -- registers r/w via wishbone" << endl;\r
+ QList<BlockParameter*> listWB = reference->getWishboneParameters();\r
+ for(i=0;i<listWB.size()-1;i++) {\r
+ out << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
+ }\r
+ out << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
+ }\r
+\r
+\r
+ int count = 0;\r
+ foreach(AbstractInterface* iface, getInterfaces()) {\r
+ if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++;\r
+ }\r
+ // Generation of the data/control signals\r
+\r
+ int flag = 0;\r
+ bool first = true;\r
+\r
+ foreach(AbstractInterface* iface, listInputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Data) {\r
+ if (first) {\r
+ out << indent << " -- input data ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listInputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Control) {\r
+ if (first) {\r
+ out << indent << " -- input control ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listOutputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Data) {\r
+ if (first) {\r
+ out << indent << " -- output data ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listOutputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Control) {\r
+ if (first) {\r
+ out << indent << " -- output control ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listBidirs) {\r
+ if(iface->getPurpose() == AbstractInterface::Data) {\r
+ if (first) {\r
+ out << indent << " -- bidirs data ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ out << indent << " );" << endl << endl;\r
+\r
+}\r
+\r
+void FunctionalBlock::generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception) {\r
+ QString expr;\r
+ QString code = elt.text();\r
+ cout << qPrintable(code) << endl;\r
+ out << "architecture rtl of " << name << " is" << endl;\r
+\r
+ QStringList listLine = code.split("\n");\r
+ for(int i =0; i < listLine.size(); i++) {\r
+ QString line = listLine.at(i).simplified();\r
+\r
+ /*\r
+ if(listLine.at(i).contains(QRegularExpression("@foreach{"))) {\r
+ while(listLine.at(i).compare("@endforeach") != -1) {\r
+ expr = expr + listLine.at(i) + '\n';\r
+ i++;\r
+ }\r
+ expr = expr + listLine.at(i);\r
+ out << evalComplex(expr, 1) << '\n';\r
+ }\r
+ if(listLine.at(i).contains(QRegularExpression("@caseeach{"))) {\r
+ while(listLine.at(i).compare("@endcaseeach") != -1) {\r
+ expr = expr + listLine.at(i) + '\n';\r
+ i++;\r
+ }\r
+ expr = expr + listLine.at(i);\r
+ out << evalComplex(expr, 2) << '\n';\r
+ }\r
+*/\r
+ if(line.contains("@{")) {\r
+ out << line << endl;\r
+ }\r
+ }\r
+}\r
+\r
+void FunctionalBlock::generateController(QTextStream &out) throw(Exception) {\r
+ \r
+}\r
+\r