+void Dispatcher::generateVHDL(Context context) throw(Exception) {
+ static QString fctName = "Dispatcher::generateVHDL()";
+#ifdef DEBUG_FCTNAME
+ cout << "call to " << qPrintable(fctName) << endl;
+#endif
+ /* NB: only called in Design context */
+ if (context != Design) {
+ cout << "Abnormal case: call to " << qPrintable(fctName) << " not in Design context" << endl;
+ return;
+ }
+
+
+ QDir baseDir(params->projectPath);
+ QDir srcDir(params->projectPath+"/src");
+
+ if (!baseDir.exists()) {
+ cerr << "Project path " << qPrintable(params->projectPath) << " no longer exists. First, recreate it and put the project file within. Then retry to generate." << endl;
+ return;
+ }
+
+ if (srcDir.exists()) {
+ srcDir.removeRecursively();
+ }
+ baseDir.mkdir("src");
+
+ if (! baseDir.exists("testbench")) {
+ baseDir.mkdir("testbench");
+ }
+ if (! baseDir.exists("Makefile")) {
+ QFile make("/home/sdomas/Projet/Blast/code/blast/Makefile-isim");
+ QString dest = params->projectPath;
+ dest += "/Makefile";
+ make.copy(dest);
+ }
+
+ // generate VHDL + copying external resources
+ QString dest = params->projectPath;
+ dest += "/src/";
+ try {
+ params->getGraph()->generateVHDL(dest);
+
+ QList<QString> extResources = params->getGraph()->getExternalResources();
+ foreach(QString name, extResources) {
+ cout << qPrintable(name) << endl;
+ QList<ExternalResource*> lstRes = params->searchResourceByName(name);
+ foreach(ExternalResource* res, lstRes) {
+ QFile resFile(res->getFile());
+ QFileInfo info(res->getFile());
+ QString destFile = dest+info.fileName();
+ cout << "copying " << qPrintable(res->getFile()) << " into " << qPrintable(destFile) << endl;
+ resFile.copy(destFile);
+ }
+ }
+ }
+ catch(Exception e) {
+ throw(e);
+ }
+ // generate testbench
+ dest = params->projectPath;
+ dest += "/testbench/";
+ dest += params->projectName;
+ dest += "_tb.vhd";
+ try {
+ params->getGraph()->generateTestbench(params->projectName, dest);
+ }
+ catch(Exception e) {
+ throw(e);
+ }
+
+ // creating parameters file
+ QString paramName = params->projectPath+"/params-isim.txt";
+ QFile paramFile(paramName);
+ if (!paramFile.open(QIODevice::WriteOnly)) {
+ throw(Exception(PROJECTPATH_NOACCESS));
+ }
+ QTextStream out(¶mFile);
+ out << "PROJECT_NAME := " << params->projectName << endl << endl;
+ out << "SRC_DIR := src" << endl;
+ out << "TB_DIR := testbench" << endl << endl;
+ out << "VHDL_SRC := ";
+ QStringList filter;
+ filter << "*.vhd" ;
+ srcDir.setNameFilters(filter);
+ QStringList listVHDL = srcDir.entryList();
+ for(int j=0;j<listVHDL.size();j++) {
+ if (j > 0) {
+ out << "\t";
+ }
+ out << "$(SRC_DIR)/" << qPrintable(listVHDL.at(j));
+ if (j != listVHDL.size()-1) {
+ out << " \\";
+ }
+ out << endl;
+ }
+ out << endl;
+ out << "VL_SRC := ${XILINX}/verilog/src/glbl.v" << endl << endl;
+ out << "TB_SRC := $(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl;
+ out << "SIMU_EXE := $(PROJECT_NAME)_tb" << endl << endl;
+
+ paramFile.close();
+
+ QString msg = "VHDL generation completed successfully. Go to ";
+ msg += params->projectPath+" and type the following commands to launch a simulation:\n";
+ msg += "\tmake clean\n";
+ msg += "\tmake\n";
+ msg += "\tmake view\n";
+ QMessageBox::information(mainWindow,"VHDL generation", msg, QMessageBox::Ok);
+
+}
+
+void Dispatcher::generateBlockVHDL(Context context, BoxItem *item){
+ static QString fctName = "Dispatcher::generateBlockVHDL()";
+#ifdef DEBUG_FCTNAME
+ cout << "call to " << qPrintable(fctName) << endl;
+#endif
+ /* NB: only called in Design context */
+ if (context != Design) {
+ cout << "Abnormal case: call to " << qPrintable(fctName) << " not in Design context" << endl;
+ return;
+ }
+
+
+ if (item->getRefBlock()->isFunctionalBlock()) {
+ FunctionalBlock* block = AB_TO_FUN(item->getRefBlock());
+ try {
+ block->generateVHDL(params->projectPath);
+ }
+ catch(Exception e) {
+ cout << qPrintable(e.getMessage()) << endl;
+ }
+ }
+}
+
+void Dispatcher::renameFunctionalBlock(Context context, BoxItem *item){
