finished VHDL gen. (but have to test further

[blast.git] / AbstractBlock.cpp

diff --git a/AbstractBlock.cpp b/AbstractBlock.cpp
index 3bb808ead3a61d5491e659821b8e426424e2ae3c..c1c3c38df0d9d7ab3f6e80af49070ff7121bc648 100644 (file)
--- a/AbstractBlock.cpp
+++ b/AbstractBlock.cpp
@@ -249,7 +249,7 @@ void AbstractBlock::connectClkReset() throw(Exception) {
 \r
   GroupBlock* parentBlock = AB_TO_GRP(parent);\r
 \r
-  cout << "connecting clk/rst for child " << qPrintable(name) << " of " << qPrintable(parentBlock->getName()) << endl;\r
+\r
 \r
   QList<AbstractInterface* > lstClk = getInterfaces(AbstractInterface::Input,AbstractInterface::Clock);\r
   QList<AbstractInterface* > lstRst = getInterfaces(AbstractInterface::Input,AbstractInterface::Reset);\r
@@ -273,10 +273,12 @@ void AbstractBlock::connectClkReset() throw(Exception) {
       fromClk = AI_TO_CON(clkrstgen->getIfaceFromName("clk"));\r
       fromRst = AI_TO_CON(clkrstgen->getIfaceFromName("reset"));\r
     }\r
+    cout << "connecting clk/rst for " << qPrintable(name) << " to clkrstgen" << endl;\r
   }\r
   else {\r
     fromClk = AI_TO_CON(parentBlock->getIfaceFromName("clk"));\r
     fromRst = AI_TO_CON(parentBlock->getIfaceFromName("reset"));\r
+    cout << "connecting clk/rst for child " << qPrintable(name) << " of " << qPrintable(parentBlock->getName()) << endl;\r
   }\r
   if ((fromClk == NULL) || (fromRst == NULL)) {\r
     throw(Exception(IFACE_GROUP_NOCLKRST,parentBlock));\r
@@ -284,6 +286,8 @@ void AbstractBlock::connectClkReset() throw(Exception) {
   else {\r
     fromClk->connectTo(toClk);\r
     fromRst->connectTo(toRst);\r
+    cout << "connection done between " << qPrintable(toClk->getConnectedFrom()->getOwner()->getName()) << "/" << qPrintable(toClk->getConnectedFrom()->getName());\r
+    cout << " and " << qPrintable(toClk->getOwner()->getName()) << "/" << qPrintable(toClk->getName()) << endl;\r
   }\r
 }\r
 \r
@@ -308,7 +312,7 @@ void AbstractBlock::generateComponent(QTextStream& out, bool hasController) thro
   catch(Exception e) {\r
     throw(e);\r
   }\r
-  out << "  end component " << endl << endl;\r
+  out << "  end component; " << endl << endl;\r
 }\r
 \r
 \r