finished VHDL gen. (but have to test further

[blast.git] / AbstractInterface.cpp

diff --git a/AbstractInterface.cpp b/AbstractInterface.cpp
index 6c51907dc047bd9e89702cac62d696821ca8386c..39e672dbba48223eff149bb37e02a8103b446bd2 100644 (file)
--- a/AbstractInterface.cpp
+++ b/AbstractInterface.cpp
@@ -298,7 +298,17 @@ QString AbstractInterface::toVHDL(int context, int flags) throw(Exception) {
   QString ret="";
 
   bool ok;
-  cout << "iface " << qPrintable(name) << " must be evaluated to vhdl :" << qPrintable(width) << " with type = " << qPrintable(getTypeString()) << endl;
+  //cout << "iface " << qPrintable(name) << " must be evaluated to vhdl :" << qPrintable(width) << " with type = " << qPrintable(getTypeString()) << endl;
+
+  if (context == Instance) {
+    if (direction == Output) {
+      ret = "from_"+owner->getName()+"_"+name;
+    }
+    else if (direction == InOut) {
+      ret = "fromto_"+owner->getName()+"_"+name;
+    }
+    return ret;
+  }
 
   // create the width part
   QString widthStr = "";
@@ -411,10 +421,15 @@ QString AbstractInterface::toVHDL(int context, int flags) throw(Exception) {
     ret += widthStr;
   }
   else if (context == Signal) {
-    ret = widthStr;
-  }
-  else if (context == Architecture) {
-
+    if (direction == Output) {
+      ret = "from_"+owner->getName()+"_"+name+" : "+widthStr;
+    }
+    else if (direction == InOut) {
+      ret = "fromto_"+owner->getName()+"_"+name+" : "+widthStr;
+    }
+    else if (direction == Input) {
+      ret = owner->getName()+"_"+name+" : "+widthStr;
+    }
   }
 
   return ret;