finished VHDL gen. (but have to test further

[blast.git] / BoxItem.cpp

diff --git a/BoxItem.cpp b/BoxItem.cpp
index 85a1c9fb13633078842e7d64c6ef5d409a7d393a..9ff42a88f7feb96f3f4d7ac413f870c2fe778e73 100644 (file)
--- a/BoxItem.cpp
+++ b/BoxItem.cpp
@@ -791,6 +791,17 @@ void BoxItem::loadFunctional(QDomElement funcElement) throw(Exception) {
       functionalBlock->addInterface(ctlIface);
     }    
   }
       functionalBlock->addInterface(ctlIface);
     }    
   }

+  // connect clk and rst to group clk/rst or to clkrstgen
+  if ((name != "clkrstgen") && (parentGroupBlock != NULL)) {
+    try {
+      functionalBlock->connectClkReset();
+    }
+    catch(Exception e) {
+      AbstractBlock* source = (AbstractBlock *)(e.getSource());
+      cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl;
+      throw(e);
+    }
+  }

   
   // creating InterfaceItem
   initInterfaceItems();
   
   // creating InterfaceItem
   initInterfaceItems();