finished VHDL gen

[blast.git] / GroupBlock.cpp

diff --git a/GroupBlock.cpp b/GroupBlock.cpp
index 9a8bb0f857df75dd5843ad5069cc80aa27f852fb..ab76563048265cd375aabeaeecff9a6d0f606f7b 100644 (file)
--- a/GroupBlock.cpp
+++ b/GroupBlock.cpp
@@ -6,6 +6,7 @@
 #include "string.h"
 #include <sstream>
 #include "Parameters.h"
 #include "string.h"
 #include <sstream>
 #include "Parameters.h"

+#include "DelayInputModifier.h"

 
 int GroupBlock::counter = 1;
 
 
 int GroupBlock::counter = 1;
 


@@ -21,8 +22,17 @@ GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) :  AbstractBlock()
     // creating clk/rst interfaces
     clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock);
     rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset);
     // creating clk/rst interfaces
     clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock);
     rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset);

-    addInterface(clk);
-    addInterface(rst);    
+    addInterface(clk);    
+    addInterface(rst);
+
+    try {
+      connectClkReset();
+    }
+    catch(Exception e) {
+      AbstractBlock* source = (AbstractBlock *)(e.getSource());
+      cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl;
+      throw(e);
+    }

   }
   else {
     topGroup = true;
   }
   else {
     topGroup = true;


@@ -267,11 +277,20 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) {
   }
 }
 
   }
 }
 

+QList<QString> GroupBlock::getExternalResources() {
+
+  QList<QString> list;
+  foreach(AbstractBlock* block, blocks) {
+    list.append(block->getExternalResources());
+  }
+  return list;
+}
+

 void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
 
   QString coreFile = "";
 
 void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
 
   QString coreFile = "";
 

-  coreFile = path;
+  coreFile = path;  

   coreFile.append(Parameters::normalizeName(name));
   coreFile.append(".vhd");
 
   coreFile.append(Parameters::normalizeName(name));
   coreFile.append(".vhd");
 


@@ -290,6 +309,10 @@ void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
     generateLibraries(outCore,dummyElt);
     generateEntity(outCore);
     generateArchitecture(outCore,dummyElt);
     generateLibraries(outCore,dummyElt);
     generateEntity(outCore);
     generateArchitecture(outCore,dummyElt);

+
+    foreach(AbstractBlock* block, blocks) {
+      block->generateVHDL(path);
+    }

   }
   catch(Exception err) {
     throw(err);
   }
   catch(Exception err) {
     throw(err);


@@ -420,6 +443,38 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
 
   out << "architecture rtl of " << name << " is " << endl << endl;
 
 
   out << "architecture rtl of " << name << " is " << endl << endl;
 

+  // generate type for delays, if needed.
+  QList<int> modWidth;
+  foreach(AbstractBlock* block, blocks) {
+    QList<AbstractInterface*> listCtlInputs = block->getControlInputs();
+    foreach(AbstractInterface* iface, listCtlInputs) {
+      ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+      AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+      if (modifier != NULL) {
+        ConnectedInterface* connIface = AI_TO_CON(connCtlIface->getAssociatedIface());
+        int w = connIface->getWidth();
+        if (w == -1) throw(Exception(INVALID_VALUE));
+        if (!modWidth.contains(w)) {
+          modWidth.append(w);
+        }
+      }
+    }
+  }
+  if (modWidth.size() > 0) {
+
+    out << "  -- types for modified inputs" << endl;
+    out << "  type vector_of_std_logic is array (natural range <>) of std_logic;" << endl;
+    foreach(int w, modWidth) {
+      QString mw = "";
+      mw.setNum(w);
+      QString mwm1 = "";
+      mwm1.setNum(w-1);
+      out << "  type vector_of_std_logic_vector"<< mw << " is array (natural range <>) of std_logic_vector(" << mwm1 << " downto 0);" << endl;
+    }
+    out << endl;
+  }
+
+

   // generate the components
   foreach(AbstractBlock* block, blocks) {
     try {
   // generate the components
   foreach(AbstractBlock* block, blocks) {
     try {


@@ -433,36 +488,164 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
   out << endl;
   // generate signals
   out << "  ----------------------------" << endl;
   out << endl;
   // generate signals
   out << "  ----------------------------" << endl;

-  out << "    SIGNALS" << endl;
+  out << "  --  SIGNALS" << endl;

   out << "  ----------------------------" << endl << endl;
 
   out << "  ----------------------------" << endl << endl;
 

-  out << "  -- signals from input ports of " << name << endl;
-  QList<AbstractInterface*> listInputs = getInputs();
-  foreach(AbstractInterface* iface, listInputs) {
+  // signals to synchronize inputs
+  out << "  -- signals to synchronize inputs" << endl;
+  foreach(AbstractInterface* iface, getInputs()) {

     if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
     if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {

-      ConnectedInterface* connIface = AI_TO_CON(iface);
-      QString prefixName = name+"_"+iface->getName()+"_TO_";
-      foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) {
-        QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName();
-        out << "  signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
-      }
+      QString name = iface->toVHDL(AbstractInterface::Signal,0);
+      name.replace(" : ","_sync : ");
+      out << "  signal " << name<< endl;

     }
   }
   out << endl;
     }
   }
   out << endl;

+
+  // "normal" signals

   foreach(AbstractBlock* block, blocks) {
     try {
       out << "  -- signals from output ports of " << block->getName() << endl;
       QList<AbstractInterface*> listOutputs = block->getOutputs();
       foreach(AbstractInterface* iface, listOutputs) {
         if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
   foreach(AbstractBlock* block, blocks) {
     try {
       out << "  -- signals from output ports of " << block->getName() << endl;
       QList<AbstractInterface*> listOutputs = block->getOutputs();
       foreach(AbstractInterface* iface, listOutputs) {
         if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {

-          ConnectedInterface* connIface = AI_TO_CON(iface);
-          QString prefixName = block->getName()+"_"+iface->getName()+"_TO_";
-          foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) {
-            QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName();
-            out << "  signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+          out << "  signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+        }
+        else if (block->getName() == "clkrstgen") {
+          if ((iface->getPurpose() == AbstractInterface::Clock)||(iface->getPurpose() == AbstractInterface::Reset)) {
+            out << "  signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+          }
+        }
+      }
+    }
+    catch(Exception e) {
+      throw(e);
+    }
+    out << endl;
+  }
+
+  // signal for modifiers
+  foreach(AbstractBlock* block, blocks) {
+    bool hasModif = false;
+    QList<AbstractInterface*> listCtlInputs = block->getControlInputs();
+
+    foreach(AbstractInterface* iface, listCtlInputs) {
+      ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+      AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+      if (modifier != NULL) {
+        hasModif = true;
+        break;
+      }
+    }
+    if (hasModif) {
+      try {
+        out << "  -- signals for modified input ports of " << block->getName() << endl;
+        foreach(AbstractInterface* iface, listCtlInputs) {
+          ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+          AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+          if (modifier != NULL) {
+            out << modifier->toVHDL(AbstractInputModifier::Signal,0) << endl;
+          }
+        }
+      }
+      catch(Exception e) {
+        throw(e);
+      }
+      out << endl;
+    }
+  }
+
+  out << "begin" << endl;
+
+  // generate signals that goes to the output ports
+
+  out << "  -- connections to output ports of " << name << endl;
+  QList<AbstractInterface*> listOutputs = getOutputs();
+  foreach(AbstractInterface* iface, listOutputs) {
+    if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+      ConnectedInterface* connIface = AI_TO_CON(iface);
+      ConnectedInterface* fromIface = connIface->getConnectedFrom();
+      out << "  " << connIface->getName() << " <= " << fromIface->toVHDL(AbstractInterface::Instance,0) << ";" << endl;
+    }
+  }
+
+  out << endl;
+
+
+
+  // generate instances
+  foreach(AbstractBlock* block, blocks) {
+    try {
+      out << "  " << block->getName() << "_1 : " << block->getName() << endl;
+
+      QList<BlockParameter*> listGenerics = block->getGenericParameters();
+      QList<AbstractInterface*> listInputs = block->getInputs();
+      QList<AbstractInterface*> listOutputs = block->getOutputs();
+      QList<AbstractInterface*> listBidirs = block->getBidirs();
+
+      if (!listGenerics.isEmpty()) {
+        out << "    generic map (" << endl;
+        for(i=0;i<listGenerics.size()-1;i++) {
+          out << "      " << listGenerics.at(i)->toVHDL(BlockParameter::Instance, BlockParameter::NoComma) << "," << endl;
+        }
+        out << "      " << listGenerics.at(i)->toVHDL(BlockParameter::Instance,BlockParameter::NoComma) << endl;
+        out << "    )" << endl;
+      }
+
+      out << "    port map (" << endl;
+      QString portMap = "";
+
+      for(i=0;i<listInputs.size();i++) {
+        ConnectedInterface* connIface = AI_TO_CON(listInputs.at(i));
+        ConnectedInterface* fromIface = connIface->getConnectedFrom();
+
+        if (fromIface->isFunctionalInterface()) {
+          portMap += "      " + connIface->getName() + " => ";
+          bool hasMod = false;
+          if (connIface->getPurpose() == AbstractInterface::Data) {
+            ConnectedInterface* connCtlIface = AI_TO_CON(connIface->getAssociatedIface());
+            if ((connCtlIface != NULL) && (connCtlIface->getInputModifier() != NULL)) {
+              hasMod = true;
+            }
+          }
+          else if (connIface->getPurpose() == AbstractInterface::Control) {
+            if (connIface->getInputModifier() != NULL) {
+              hasMod = true;
+            }
+          }
+          if (hasMod) {
+            portMap += connIface->getOwner()->getName()+"_"+connIface->getName()+"_mod,\n";
+          }
+          else {
+            portMap += fromIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";
+          }
+        }
+        else if (fromIface->isGroupInterface()) {
+          if ((fromIface->getOwner()->isTopGroupBlock()) && ((fromIface->getPurpose() == AbstractInterface::Data)||(fromIface->getPurpose() == AbstractInterface::Control))) {
+            portMap += "      " + connIface->getName() + " => " + fromIface->getOwner()->getName()+ "_"+ fromIface->getName() + "_sync,\n";
+          }
+          else {
+            portMap += "      " + connIface->getName() + " => " + fromIface->getName() + ",\n";

           }
         }
       }
           }
         }
       }

+      if (listOutputs.size()>0) {
+        for(i=0;i<listOutputs.size();i++) {
+          ConnectedInterface* connIface = AI_TO_CON(listOutputs.at(i));
+          portMap += "      " + connIface->getName() + " => " + connIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";
+        }
+      }
+      if (listBidirs.size()>0) {
+        for(i=0;i<listBidirs.size();i++) {
+          ConnectedInterface* connIface = AI_TO_CON(listBidirs.at(i));
+          portMap += "      " + connIface->getName() + " => " + connIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";
+        }
+      }
+      portMap.chop(2);
+      out << portMap << endl;
+
+
+      out << "    );" << endl;

     }
     catch(Exception e) {
       throw(e);
     }
     catch(Exception e) {
       throw(e);


@@ -470,6 +653,59 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
     out << endl;
   }
 
     out << endl;
   }
 

+  // generate input modifiers
+  foreach(AbstractBlock* block, blocks) {
+
+    foreach(AbstractInterface* iface, block->getControlInputs()) {
+      ConnectedInterface* connIface = AI_TO_CON(iface);
+      // check if it is connected
+      if (connIface->getConnectedFrom() == NULL) {
+        throw(Exception(IFACE_NOT_CONNECTED,this));
+      }
+      AbstractInputModifier* modifier = connIface->getInputModifier();
+      if (modifier != NULL) {
+        try {
+          out << modifier->toVHDL(AbstractInputModifier::Architecture,0) << endl;
+        }
+        catch(Exception e) {
+          throw(e);
+        }
+      }
+    }
+  }
+
+  if (topGroup) {
+    // generate input sync process
+    out << "  -- process to synchronize inputs of top group" << endl;
+    out << "sync_inputs : process(from_clkrstgen_clk,from_clkrstgen_reset)" << endl;
+    out << "  begin" << endl;
+    out << "    if from_clkrstgen_reset = '1' then" << endl;
+    foreach(AbstractInterface* iface, getInputs()) {
+      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+        if (iface->getWidth() == 0) {
+          out << "      " << name << "_" << iface->getName() << "_sync <= '0';" << endl;
+        }
+        else {
+          out << "      " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl;
+        }
+      }
+    }
+    out << "    elsif rising_edge(from_clkrstgen_clk) then" << endl;
+    foreach(AbstractInterface* iface, getInputs()) {
+      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+        if (iface->getWidth() == 0) {
+          out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+        }
+        else {
+          out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+        }
+      }
+    }
+    out << "    end if;" << endl;
+    out << "  end process sync_inputs;" << endl;
+
+    out << endl;
+  }

 
   out << "end architecture rtl;" << endl;
 }
 
   out << "end architecture rtl;" << endl;
 }