#include "ArithmeticEvaluator.h"\r
\r
\r
-FunctionalBlock::FunctionalBlock(GroupBlock *_parent, ReferenceBlock *_reference) throw(Exception) : AbstractBlock() {\r
+FunctionalBlock::FunctionalBlock(GroupBlock *_parent, ReferenceBlock *_reference, bool createIfaces) throw(Exception) : AbstractBlock() {\r
//if (! _reference->isReferenceBlock()) throw(Exception(BLOCK_INVALID_TYPE));\r
//if (! _group->isGroupBlock()) throw(Exception(BLOCK_INVALID_TYPE));\r
reference = _reference;\r
delta = -1;\r
evaluator = NULL;\r
\r
+ if (createIfaces) {\r
+ populate();\r
+ }\r
+\r
}\r
\r
FunctionalBlock::~FunctionalBlock() {\r
return true;\r
}\r
\r
-bool FunctionalBlock::isSourceBlock() {\r
+bool FunctionalBlock::isStimuliBlock() {\r
if (parent == NULL) return true;\r
return false;\r
}\r
addInterface(inter);\r
/* WARNING FOR THE FUTURE :\r
in case of there are several clock interfaces ofr that block\r
- it would be a godd idea to make the user choose which one\r
+ it would be a good idea to make the user choose which one\r
must be connected to defautl clk.\r
Presently, the first encountered is chosen\r
*/\r
} \r
}\r
}\r
-\r
- // connect clk and rst to group clk/rst or to clkrstgen\r
- if ((name != "clkrstgen") && (parent != NULL)) {\r
- try {\r
- connectClkReset();\r
- }\r
- catch(Exception e) {\r
- AbstractBlock* source = (AbstractBlock *)(e.getSource());\r
- cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl;\r
- throw(e);\r
- }\r
- }\r
}\r
\r
QString FunctionalBlock::getReferenceXmlFile() {\r
\r
cout << "create patterns for block " << qPrintable(name) << endl;\r
if (evaluator == NULL) evaluator = new ArithmeticEvaluator();\r
- if (! isGeneratorBlock()) {\r
+ if (! isSourceBlock()) {\r
try {\r
createDelta();\r
createConsumptionPattern(); \r
catch(Exception e) {\r
throw(e);\r
}\r
+ if (repeat == 0) {\r
+ // remove the last\r
+ patternOut.removeLast();\r
+ }\r
+ else {\r
// repeat just the last value in currentGroup\r
- char last = patternOut.last();\r
- //cout << "repeat last char " << repeat << " times : " << (int)last << endl;\r
- \r
- for(int i=1;i<(int)repeat;i++) {\r
- patternOut.append(last);\r
+ char last = patternOut.last();\r
+ //cout << "repeat last char " << repeat << " times : " << (int)last << endl;\r
+ for(int i=1;i<(int)repeat;i++) {\r
+ patternOut.append(last);\r
+ }\r
}\r
} \r
*offset += 1;\r
catch(Exception e) {\r
throw(e);\r
}\r
- /*\r
+ if (repeat == 0) {\r
+ QList<char> voidList;\r
+ return voidList;\r
+ }\r
+ else {\r
+ /*\r
cout << "repeat last group " << repeat << " times : ";\r
foreach (char c, currentGroup) cout <<(int)c;\r
- cout << endl; \r
+ cout << endl;\r
*/\r
- QList<char> single = patternOut;\r
- for(int i=1;i<(int)repeat;i++) {\r
- patternOut.append(single);\r
- } \r
+ QList<char> single = patternOut;\r
+ for(int i=1;i<(int)repeat;i++) {\r
+ patternOut.append(single);\r
+ }\r
+ }\r
} \r
return patternOut;\r
}\r
\r
clearOutputPattern();\r
\r
- /* case 1: the block is a generator for which output pattern\r
- must be computed for a nbExec following executions\r
- */\r
+ if (specialType != NotSpecial) {\r
+ cerr << "Abnormal case: the block is special and output pattern is computed normally" << endl;\r
+ throw(Exception(INVALID_FUNBLOCK_USE,this));\r
+ }\r
\r
- if (nbExec > 0) {\r
- cout << "computing output pattern of " << qPrintable(name) << " for " << nbExec << " executions" << endl;\r
- foreach(AbstractInterface* iface, getControlOutputs()) {\r
- FunctionalInterface* connIface = AI_TO_FUN(iface);\r
- // create output pattern\r
- QList<char>* pp = productionPattern.value(connIface);\r
- QList<char>* pattern = new QList<char>(*pp);\r
- for(int i=1;i<nbExec;i++) pattern->append(*pp);\r
- // assign pattern to interface\r
- connIface->setOutputPattern(pattern);\r
- // store it in QMap\r
- outputPattern.insert(connIface,pattern); \r
+ cout << "computing output pattern of " << qPrintable(name) << endl;\r
+\r
+ // in case of inputPattern not created, do it\r
+ if (lengthIP <= 0) {\r
+\r
+ cout << "Strange case: input pattern is not created while it is time to compute output pattern !" << endl;\r
+ // collect the input patterns for each input\r
+ try {\r
+ createInputPattern();\r
}\r
+ catch(Exception e) {\r
+ throw(e);\r
+ }\r
+ cout << "input pattern array initialized with min. len " << lengthIP << endl;\r
}\r
- else {\r
- cout << "computing output pattern of " << qPrintable(name) << endl;\r
- \r
- // in case of inputPattern not created, do it\r
- if (lengthIP <= 0) {\r
\r
- cout << "Strange case: input pattern is not created while it is time to compute output pattern !" << endl;\r
- // collect the input patterns for each input \r
- try {\r
- createInputPattern();\r
- }\r
- catch(Exception e) {\r
- throw(e);\r
+ // initialize the output pattern\r
+ lengthOP = 0;\r
+ foreach(AbstractInterface* iface, getControlOutputs()) {\r
+ FunctionalInterface* connIface = AI_TO_FUN(iface);\r
+ lengthOP = lengthIP+productionPattern.value(connIface)->size();\r
+ QList<char>* pattern = new QList<char>();\r
+ for(int i=0;i<lengthOP;i++) pattern->append(0);\r
+ connIface->setOutputPattern(pattern);\r
+ outputPattern.insert(connIface,pattern);\r
+ }\r
+ cout << "output pattern array initialized" << endl;\r
+\r
+ int clock = 0;\r
+ nbExec = 0;\r
+ // search for the beginning of the first execution.\r
+ while ((clock < lengthIP) && (! isValidDataGroup(inputPattern,clock))) clock++;\r
+ cout << "found 1st exec clock: " << clock << endl;\r
+\r
+ while (clock < lengthIP) {\r
+ // initialize counters for current execution.\r
+ int p = 0; // index in production pattern\r
+ int o = 0; // clock+o will give the clock cycle of each output group\r
+ int cip = 0; // clock+cip give the clock cycle of an input group\r
+ int ccp = 0; // ccp give a column in the consumptio pattern\r
+ int nip = 0; // number of input data groups already consumed during the current execution, used while exploring IP\r
+ int ncp = 0; // number of input data groups already consumed during the current execution, used while exploring CP\r
+ bool cannotCompleteExec = false;\r
+ for(int m=0;m<productionCounter.size();m++) {\r
+ // search for the first production in PP\r
+ while (!isValidDataGroup(productionPattern,p)) {\r
+ p += 1;\r
+ o += 1;\r
}\r
- cout << "input pattern array initialized with min. len " << lengthIP << endl;\r
- }\r
- \r
- // initialize the output pattern \r
- lengthOP = 0;\r
- foreach(AbstractInterface* iface, getControlOutputs()) {\r
- FunctionalInterface* connIface = AI_TO_FUN(iface); \r
- lengthOP = lengthIP+productionPattern.value(connIface)->size();\r
- QList<char>* pattern = new QList<char>();\r
- for(int i=0;i<lengthOP;i++) pattern->append(0);\r
- connIface->setOutputPattern(pattern);\r
- outputPattern.insert(connIface,pattern);\r
- }\r
- cout << "output pattern array initialized" << endl;\r
- \r
- int clock = 0;\r
- nbExec = 0;\r
- // search for the beginning of the first execution.\r
- while ((clock < lengthIP) && (! isValidDataGroup(inputPattern,clock))) clock++;\r
- cout << "found 1st exec clock: " << clock << endl;\r
- \r
- while (clock < lengthIP) {\r
- // initialize counters for current execution.\r
- int p = 0; // index in production pattern\r
- int o = 0; // clock+o will give the clock cycle of each output group\r
- int cip = 0; // clock+cip give the clock cycle of an input group\r
- int ccp = 0; // ccp give a column in the consumptio pattern\r
- int nip = 0; // number of input data groups already consumed during the current execution, used while exploring IP\r
- int ncp = 0; // number of input data groups already consumed during the current execution, used while exploring CP\r
- bool cannotCompleteExec = false;\r
- for(int m=0;m<productionCounter.size();m++) {\r
- // search for the first production in PP\r
- while (!isValidDataGroup(productionPattern,p)) {\r
- p += 1;\r
- o += 1;\r
+ int gap = 0; // count the number of extra null columns\r
+ // search for PC(m) valid input group in IP\r
+ while (nip < productionCounter.at(m)) {\r
+ if (clock+cip < lengthIP) {\r
+ if (isValidDataGroup(inputPattern,clock+cip)) nip += 1;\r
+ cip += 1;\r
+ gap += 1;\r
}\r
- int gap = 0; // count the number of extra null columns\r
- // search for PC(m) valid input group in IP\r
- while (nip < productionCounter.at(m)) {\r
- if (clock+cip < lengthIP) {\r
- if (isValidDataGroup(inputPattern,clock+cip)) nip += 1;\r
- cip += 1;\r
- gap += 1;\r
- }\r
- else {\r
- cannotCompleteExec = true;\r
- break;\r
- } \r
- } \r
- \r
- if (cannotCompleteExec) break; // no need to go further since the next search of input data group will lead to go outside inputPattern\r
- \r
- // search for PC(m) valid input group in IP\r
- while (ncp < productionCounter.at(m)) {\r
- if (isValidDataGroup(consumptionPattern,ccp)) ncp += 1;\r
- ccp += 1;\r
- gap -= 1;\r
+ else {\r
+ cannotCompleteExec = true;\r
+ break;\r
}\r
- o += gap; // to take into acocunt of extra null columns\r
- combinePatterns(productionPattern,p,outputPattern,clock+o);\r
- p += 1;\r
- o += 1;\r
}\r
- \r
+\r
if (cannotCompleteExec) break; // no need to go further since the next search of input data group will lead to go outside inputPattern\r
- \r
- // current exec. taken into accunt\r
- nbExec += 1;\r
- \r
- // search for the next exec.\r
- clock += 1; \r
- nip = 0;\r
- while ((clock < lengthIP) && (nip < delta)) {\r
- if (isValidDataGroup(inputPattern,clock)) nip += 1;\r
- if (nip < delta) clock += 1;\r
+\r
+ // search for PC(m) valid input group in IP\r
+ while (ncp < productionCounter.at(m)) {\r
+ if (isValidDataGroup(consumptionPattern,ccp)) ncp += 1;\r
+ ccp += 1;\r
+ gap -= 1;\r
}\r
- cout << "found exec " << nbExec << " at clock: " << clock << endl;\r
+ o += gap; // to take into acocunt of extra null columns\r
+ combinePatterns(productionPattern,p,outputPattern,clock+o);\r
+ p += 1;\r
+ o += 1;\r
}\r
- // find the last valid output data group\r
- while(! isValidDataGroup(outputPattern,lengthOP-1)) {\r
- removeDataGroup(outputPattern,lengthOP-1);\r
- lengthOP -= 1;\r
+\r
+ if (cannotCompleteExec) break; // no need to go further since the next search of input data group will lead to go outside inputPattern\r
+\r
+ // current exec. taken into accunt\r
+ nbExec += 1;\r
+\r
+ // search for the next exec.\r
+ clock += 1;\r
+ nip = 0;\r
+ while ((clock < lengthIP) && (nip < delta)) {\r
+ if (isValidDataGroup(inputPattern,clock)) nip += 1;\r
+ if (nip < delta) clock += 1;\r
}\r
+ cout << "found exec " << nbExec << " at clock: " << clock << endl;\r
+ }\r
+ // find the last valid output data group\r
+ while(! isValidDataGroup(outputPattern,lengthOP-1)) {\r
+ removeDataGroup(outputPattern,lengthOP-1);\r
+ lengthOP -= 1;\r
+ }\r
+\r
+ // clear input pattern\r
+ clearInputPattern();\r
+\r
+ setOutputPatternComputed(true);\r
\r
- // clear input pattern\r
- clearInputPattern();\r
- } \r
}\r
\r
/*\r
return triggers.size();\r
}\r
\r
+QList<QString> FunctionalBlock::getExternalResources() {\r
+\r
+ BlockImplementation* impl = reference->getImplementations().at(0); // for now only take first impl available\r
+ QList<QString> list = impl->getResources();\r
+ foreach(QString s, list) {\r
+ cout << qPrintable(s) << " ";\r
+ }\r
+ cout << endl;\r
+\r
+ return list;\r
+}\r
+\r
+\r
void FunctionalBlock::generateVHDL(const QString& path) throw(Exception){\r
\r
- BlockImplementation* impl = reference->getImplementations().at(0); // for now only take first impl available\r
+ BlockImplementation* impl = reference->getImplementations().at(0); // for now only take first impl available \r
+\r
QFile implFile(impl->getXmlFile());\r
\r
// reading in into QDomDocument\r
QString mail = eltAuthor.attribute("mail","");\r
out << "-- Author(s) : "<<firstName+" "<<lastName<<" ("<<mail<<")" << endl;\r
out << "--" << endl;\r
- QDomElement eltDate = eltAuthor.nextSiblingElement("date");\r
- QString crea = eltDate.attribute("creation","");\r
+ QDomElement eltLog = eltAuthor.nextSiblingElement("log");\r
+ QString crea = eltLog.attribute("creation","");\r
out << "-- Creation Date : "<<crea<< endl;\r
out << "--" << endl;\r
- QDomElement eltRelated = eltDate.nextSiblingElement("related_files");\r
- QString relateds = eltRelated.attribute("list","");\r
- out << "-- Related files :\n"<<relateds<<endl;\r
- out << "--" << endl;\r
- QDomElement eltDesc = eltRelated.nextSiblingElement("description");\r
- QDomElement desc = eltDesc.firstChildElement();\r
- QString descTxt = desc.text();\r
- out << "-- Decription :\n"<<descTxt<<endl;\r
+ QDomNodeList listModifs = eltLog.elementsByTagName("modification");\r
+ for(int j=0;j<listModifs.length();j++) {\r
+ QDomNode nodeModif = listModifs.at(j);\r
+ QDomElement eltModif = nodeModif.toElement();\r
+ }\r
+ out << "-- Description : " << endl;\r
+ out << reference->getDescription() << endl;\r
out << "--" << endl;\r
- QDomElement eltNote = eltDesc.nextSiblingElement("description");\r
+ QDomElement eltNote = eltLog.nextSiblingElement("notes");\r
QDomElement note = eltNote.firstChildElement();\r
QString noteTxt = note.text();\r
- out << "-- Note :\n"<<noteTxt<<endl;\r
+ out << "-- Notes :\n"<<noteTxt<<endl;\r
out << "--" << endl;\r
for(int i = 0; i < 50; i++) {\r
out << "--";\r
QDomElement eltPack = nodePack.toElement();\r
QString namePack = eltPack.attribute("name","none");\r
QString usePack = eltPack.attribute("use","none");\r
- out << "use " << nameLib << "." << namePack << "." << usePack << endl;\r
+ out << "use " << nameLib << "." << namePack << "." << usePack << ";" << endl;\r
}\r
out << endl;\r
}\r
\r
out << indent << " port (" << endl;\r
\r
+ QString ports = "";\r
+ QTextStream outPorts(&ports);\r
+\r
// Generation of the clk & rst signals\r
- out << indent << " -- clk/rst" << endl;\r
+ outPorts << indent << " -- clk/rst" << endl;\r
foreach(AbstractInterface* iface, listInputs) {\r
if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
- out << indent << " " << iface->getName() << " : in std_logic;" << endl;\r
+ outPorts << indent << " " << iface->getName() << " : in std_logic;" << endl;\r
}\r
}\r
foreach(AbstractInterface* iface, listOutputs) {\r
if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
- out << indent << " " << iface->getName() << " : out std_logic;" << endl;\r
+ outPorts << indent << " " << iface->getName() << " : out std_logic;" << endl;\r
}\r
}\r
\r
if (hasController) {\r
// Generation of the wishbone signals\r
- out << indent << " -- registers r/w via wishbone" << endl;\r
+ outPorts << indent << " -- registers r/w via wishbone" << endl;\r
QList<BlockParameter*> listWB = reference->getWishboneParameters();\r
for(i=0;i<listWB.size()-1;i++) {\r
- out << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
+ outPorts << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
}\r
- out << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
+ outPorts << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
}\r
\r
-\r
- int count = 0;\r
- foreach(AbstractInterface* iface, getInterfaces()) {\r
- if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++;\r
- }\r
// Generation of the data/control signals\r
\r
- int flag = 0;\r
- bool first = true;\r
-\r
- foreach(AbstractInterface* iface, listInputs) {\r
- if(iface->getPurpose() == AbstractInterface::Data) {\r
- if (first) {\r
- out << indent << " -- input data ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ QList<AbstractInterface*> listIface = getInterfaces(AbstractInterface::Input, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- input data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
}\r
}\r
- first = true;\r
- foreach(AbstractInterface* iface, listInputs) {\r
- if(iface->getPurpose() == AbstractInterface::Control) {\r
- if (first) {\r
- out << indent << " -- input control ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ listIface = getInterfaces(AbstractInterface::Input, AbstractInterface::Control);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- input control ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
}\r
}\r
- first = true;\r
- foreach(AbstractInterface* iface, listOutputs) {\r
- if(iface->getPurpose() == AbstractInterface::Data) {\r
- if (first) {\r
- out << indent << " -- output data ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ listIface = getInterfaces(AbstractInterface::Output, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- output data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
}\r
}\r
- first = true;\r
- foreach(AbstractInterface* iface, listOutputs) {\r
- if(iface->getPurpose() == AbstractInterface::Control) {\r
- if (first) {\r
- out << indent << " -- output control ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ listIface = getInterfaces(AbstractInterface::Output, AbstractInterface::Control);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- output control ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
}\r
}\r
- first = true;\r
- foreach(AbstractInterface* iface, listBidirs) {\r
- if(iface->getPurpose() == AbstractInterface::Data) {\r
- if (first) {\r
- out << indent << " -- bidirs data ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ listIface = getInterfaces(AbstractInterface::InOut, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- bidirs data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
}\r
}\r
+\r
+ ports.chop(2);\r
+ ports += "\n";\r
+ out << ports;\r
out << indent << " );" << endl << endl;\r
\r
}\r
\r
void FunctionalBlock::generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception) {\r
+ QRegularExpression rxPort("@\\{([a-zA-Z0-9_]+)\\}");\r
QString expr;\r
QString code = elt.text();\r
- cout << qPrintable(code) << endl;\r
+ //cout << qPrintable(code) << endl;\r
out << "architecture rtl of " << name << " is" << endl;\r
\r
QStringList listLine = code.split("\n");\r
}\r
*/\r
if(line.contains("@{")) {\r
- out << line << endl;\r
+ QMap<QString,QString> modifs;\r
+ //cout << qPrintable(line) << endl;\r
+ QRegularExpressionMatchIterator matchPort = rxPort.globalMatch(line);\r
+ while(matchPort.hasNext()) {\r
+ QRegularExpressionMatch m = matchPort.next();\r
+ QString refName = m.captured(1);\r
+ AbstractInterface* refIface = reference->getIfaceFromName(refName);\r
+ QString funName = getIfaceUserName(refIface);\r
+ if (!funName.isEmpty()) {\r
+ modifs.insert(m.captured(0),funName);\r
+ //cout << "replace " << qPrintable(refIface->getName()) << " by " << qPrintable(funIface->getName()) << endl;\r
+ }\r
+ }\r
+ QMapIterator<QString,QString> iterM(modifs);\r
+ while(iterM.hasNext()) {\r
+ iterM.next();\r
+ QString oldName = iterM.key();\r
+ QString newName = iterM.value();\r
+ line.replace(oldName,newName);\r
+ }\r
}\r
+ out << line << endl;\r
}\r
+\r
+ out << "end rtl;" << endl;\r
}\r
\r
void FunctionalBlock::generateController(QTextStream &out) throw(Exception) {\r
\r
}\r
\r
+QString FunctionalBlock::getIfaceUserName(AbstractInterface* refIface) {\r
+\r
+ if (! refIface->isReferenceInterface()) return "";\r
+\r
+ AbstractInterface* funcIface = NULL;\r
+\r
+ if (refIface->getDirection() == AbstractInterface::Input) {\r
+ foreach(AbstractInterface* iface, getInputs()) {\r
+ FunctionalInterface* fi = AI_TO_FUN(iface);\r
+ if (fi->getReference() == refIface) {\r
+ funcIface = iface;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else if (refIface->getDirection() == AbstractInterface::Output) {\r
+ foreach(AbstractInterface* iface, getOutputs()) {\r
+ FunctionalInterface* fi = AI_TO_FUN(iface);\r
+ if (fi->getReference() == refIface) {\r
+ funcIface = iface;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else if (refIface->getDirection() == AbstractInterface::InOut) {\r
+ foreach(AbstractInterface* iface, getBidirs()) {\r
+ FunctionalInterface* fi = AI_TO_FUN(iface);\r
+ if (fi->getReference() == refIface) {\r
+ funcIface = iface;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ if (funcIface == NULL) return "";\r
+\r
+ return funcIface->getName();\r
+}\r
+\r
