finished testbench generation

[blast.git] / VHDLConverter.cpp

diff --git a/VHDLConverter.cpp b/VHDLConverter.cpp
index 88b371f01440213679c51c2b42927ba2486a97c5..275ceb47e0a5dce4a12463aeaaff91da0ed9e780 100644 (file)
--- a/VHDLConverter.cpp
+++ b/VHDLConverter.cpp
@@ -359,14 +359,18 @@ void VHDLConverter::readPorts(QTextStream &in) throw(Exception) {
 void VHDLConverter::readArchitecture(QTextStream &in) throw(Exception) {\r
 \r
   QString line = "";\r
-  QString endLine = "end "+archName;\r
+  QString endLine1 = "end "+archName;\r
+  QString endLine2 = "end architecture "+archName;\r
+  bool stop = false;\r
 \r
-  while (!line.startsWith(endLine)) {\r
+  while (!stop) {\r
     line = in.readLine();\r
     if (!line.isEmpty()) line = line.simplified();\r
     archLines.append(line);\r
-  }\r
-  \r
+    if ((line.startsWith(endLine1)) || (line.startsWith(endLine2)) ) {\r
+      stop = true;\r
+    }\r
+  }  \r
 }\r
 \r
 // This function opens a VHDL file and get the informations about the entity :\r