<block_impl ref_name="apf27-wb-master.xml" ref_md5="">
<comments>
<author firstname="stephane" lastname="Domas" mail="sdomas@univ-fcomte.fr" />
<block_impl ref_name="apf27-wb-master.xml" ref_md5="">
<comments>
<author firstname="stephane" lastname="Domas" mail="sdomas@univ-fcomte.fr" />
- <date creation="2015-04-27" />
- <related_files list="interconn.vhd,clkrstgen.vhd"/>
- <description>
- This component is an interface between i.MX signals
- and the interconnector component.
- </description>
+ <log creation="2018-05-02">
+ <modification id="1" date="2018-05-02">
+ changed to comply with new structure
+ </modification>
+ </log>
- On i.MX<->FPGA connection : the WEIM part of i.MX has a 16 bits bus address
- but only [1:12] bits are connected to FPGA pins. From the i.MX point of view
- it means that reading in memory mapped address 0x0002 or 0x0003 gives the same
- result since the LSB bit of the address is not transmited.
-
- These 12 bits are forwarded to the interconnector which is responsible to
- determine for what IP the data and addr signals must be routed.
-
+ On i.MX<->FPGA connection : the WEIM part of i.MX has a 16 bits bus address
+ but only [1:12] bits are connected to FPGA pins. From the i.MX point of view
+ it means that reading in memory mapped address 0x0002 or 0x0003 gives the same
+ result since the LSB bit of the address is not transmited.
+
+ These 12 bits are forwarded to the interconnector which is responsible to
+ determine for what IP the data and addr signals must be routed.
