finished conn mode of library

[blast.git] / AbstractBlock.h

diff --git a/AbstractBlock.h b/AbstractBlock.h
index 042a59883b90d4bcf5339a8f491ce3e0ca98234d..fe3f90e392c67c511d86d7060ba07d7eb62b18fe 100644 (file)
--- a/AbstractBlock.h
+++ b/AbstractBlock.h
@@ -4,6 +4,7 @@
 #include <iostream>\r
 \r
 #include <QtCore>\r
+#include <QtXml>\r
 \r
 #include "AbstractInterface.h"\r
 class AbstractInterface;\r
@@ -20,8 +21,10 @@ class AbstractBlock {
 \r
 public:  \r
       \r
+  enum BlockVHDLContext {AnyContext = 0, Entity = 1, Component = 2, Architecture = 3 }; // NB : 3 is when creating an instance of the block that owns this iface\r
+\r
   AbstractBlock();\r
-  AbstractBlock(const QString& _name);\r
+  //AbstractBlock(const QString& _name);\r
   virtual ~AbstractBlock();\r
 \r
   // getters\r
@@ -30,7 +33,7 @@ public:
   inline QList<BlockParameter *> getParameters() { return params; }\r
   inline QList<AbstractInterface*> getInputs() { return inputs; }\r
   inline QList<AbstractInterface*> getOutputs() { return outputs; }\r
-  inline QList<AbstractInterface*> getBidirs() { return bidirs; }\r
+  inline QList<AbstractInterface*> getBidirs() { return bidirs; }  \r
   QList<BlockParameter *> getUserParameters();\r
   QList<BlockParameter *> getGenericParameters();\r
   QList<BlockParameter *> getPortParameters();\r
@@ -56,7 +59,18 @@ public:
   bool isWBConfigurable();\r
 \r
   // others\r
-  static QString normalizeName(const QString& name);\r
+\r
+  /*!\r
+   * \brief connectClkReset connects the clock and reset inputs to a clkrstgen block or the the group ifaces\r
+   * \param idBlockClk is the id of the clock interface (there may be severals)\r
+   * \param idGen is the id of the clkrstgen block\r
+  */\r
+  void connectClock(QString clkName, int idGen = 0) throw(Exception);\r
+  void connectReset(QString rstName, int idGen = 0) throw(Exception);\r
+  virtual QList<QString> getExternalResources() = 0; // returns the list of all external files needed for VHDL generation\r
+  virtual void generateVHDL(const QString& path) throw(Exception) = 0; // main entry to generate the VHDL code\r
+  void generateComponent(QTextStream& out, bool hasController=false) throw(Exception); // generate the component using reference\r
+  void generateEntity(QTextStream& out, bool hasController=false) throw(Exception); // generate the entity using reference\r
 \r
   virtual void parametersValidation(QList<AbstractBlock*>* checkedBlocks, QList<AbstractBlock*>* blocksToConfigure) = 0; // ugly but usefull   \r
 \r
@@ -101,6 +115,11 @@ protected:
   // NB: only GroupBlock and FunctionalBlock have a real parent, except sources that have no parents\r
   AbstractBlock* parent;\r
 \r
+  virtual void generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception) = 0; // generates comments from <comments> element\r
+  virtual void generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception) = 0; // generates libraries from <libraries> element  \r
+  virtual void generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception) = 0; // generate the architecture using <architecture> element\r
+  virtual void generateController(QTextStream& out) throw(Exception) = 0; // generate the wishbone controller of the block\r
+  virtual void generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController=false) throw(Exception) = 0; // generate the entity/compo body using reference\r
 \r
 };\r
 \r