finished VHDL gen

[blast.git] / AbstractBlock.cpp

diff --git a/AbstractBlock.cpp b/AbstractBlock.cpp
index cdde69fcdc9b6051c396c62559a84f4151b60e04..c1c3c38df0d9d7ab3f6e80af49070ff7121bc648 100644 (file)
--- a/AbstractBlock.cpp
+++ b/AbstractBlock.cpp
@@ -3,16 +3,22 @@
 #include <QMessageBox>\r
 #include "AbstractInterface.h"\r
 #include "BlockParameter.h"\r
+#include "Parameters.h"\r
+#include "GroupBlock.h"\r
+#include "ConnectedInterface.h"\r
+\r
 \r
 AbstractBlock::AbstractBlock() {\r
   name = "";\r
   parent = NULL;\r
 }\r
 \r
+/*\r
 AbstractBlock::AbstractBlock(const QString& _name) {\r
-  name = normalizeName(_name);\r
+  name = Parameters::normalizeName(_name);\r
   parent = NULL;\r
 }\r
+*/\r
 \r
 AbstractBlock::~AbstractBlock() {\r
 \r
@@ -25,7 +31,7 @@ AbstractBlock::~AbstractBlock() {
 }\r
 \r
 void AbstractBlock::setName(const QString& str) {\r
-  name = normalizeName(str);\r
+  name = Parameters::normalizeName(str);\r
 }\r
 \r
 void AbstractBlock::setParent(AbstractBlock* _parent) {\r
@@ -53,10 +59,12 @@ bool AbstractBlock::isSourceBlock() {
 }\r
 /* NB: a generator is a block that has no data inputs\r
  * and has at least one data output.\r
+ * By the way, blokcs that have no data input/output\r
+ * (like clkrstgen) are not generators !\r
  */\r
 bool AbstractBlock::isGeneratorBlock() {\r
   if (getDataInputs().size() > 0) return false;\r
-  \r
+  if (getDataOutputs().size() == 0) return false;\r
   return true;\r
 }\r
 \r
@@ -235,11 +243,76 @@ QList<BlockParameter *> AbstractBlock::getWishboneParameters() {
   return lst;\r
 }\r
 \r
-QString AbstractBlock::normalizeName(const QString &name) {\r
-  QString s = name;\r
-  s.replace(QRegularExpression("[^a-zA-Z0-9_]"),"_");\r
-  s.replace(QRegularExpression("[_]+"),"_");\r
-  return s;\r
+\r
+\r
+void AbstractBlock::connectClkReset() throw(Exception) {\r
+\r
+  GroupBlock* parentBlock = AB_TO_GRP(parent);\r
+\r
+\r
+\r
+  QList<AbstractInterface* > lstClk = getInterfaces(AbstractInterface::Input,AbstractInterface::Clock);\r
+  QList<AbstractInterface* > lstRst = getInterfaces(AbstractInterface::Input,AbstractInterface::Reset);\r
+\r
+  if ((lstClk.isEmpty()) || (lstRst.isEmpty())) {\r
+    throw(Exception(IFACE_GROUP_NOCLKRST,this));\r
+  }\r
+\r
+  ConnectedInterface* toClk = AI_TO_CON(lstClk.at(0));\r
+  ConnectedInterface* toRst = AI_TO_CON(lstRst.at(0));\r
+\r
+  ConnectedInterface* fromClk = NULL;\r
+  ConnectedInterface* fromRst = NULL;\r
+\r
+  if (parentBlock->isTop()) {\r
+    AbstractBlock* clkrstgen = parentBlock->getFunctionalBlockByName("clkrstgen");\r
+    if (clkrstgen == NULL) {\r
+      throw(Exception(IFACE_TOP_NOCLKRSTGEN,this));\r
+    }\r
+    else {\r
+      fromClk = AI_TO_CON(clkrstgen->getIfaceFromName("clk"));\r
+      fromRst = AI_TO_CON(clkrstgen->getIfaceFromName("reset"));\r
+    }\r
+    cout << "connecting clk/rst for " << qPrintable(name) << " to clkrstgen" << endl;\r
+  }\r
+  else {\r
+    fromClk = AI_TO_CON(parentBlock->getIfaceFromName("clk"));\r
+    fromRst = AI_TO_CON(parentBlock->getIfaceFromName("reset"));\r
+    cout << "connecting clk/rst for child " << qPrintable(name) << " of " << qPrintable(parentBlock->getName()) << endl;\r
+  }\r
+  if ((fromClk == NULL) || (fromRst == NULL)) {\r
+    throw(Exception(IFACE_GROUP_NOCLKRST,parentBlock));\r
+  }\r
+  else {\r
+    fromClk->connectTo(toClk);\r
+    fromRst->connectTo(toRst);\r
+    cout << "connection done between " << qPrintable(toClk->getConnectedFrom()->getOwner()->getName()) << "/" << qPrintable(toClk->getConnectedFrom()->getName());\r
+    cout << " and " << qPrintable(toClk->getOwner()->getName()) << "/" << qPrintable(toClk->getName()) << endl;\r
+  }\r
+}\r
+\r
+void AbstractBlock::generateEntity(QTextStream& out, bool hasController) throw(Exception) {\r
+\r
+  out << "entity " << name << " is" << endl;\r
+  try {\r
+    generateEntityOrComponentBody(out, 0, hasController);\r
+  }\r
+  catch(Exception e) {\r
+    throw(e);\r
+  }\r
+  out << "end entity " << name << ";" << endl << endl;\r
+}\r
+\r
+void AbstractBlock::generateComponent(QTextStream& out, bool hasController) throw(Exception) {\r
+\r
+  out << "  component " << name << " is" << endl;\r
+  try {\r
+    generateEntityOrComponentBody(out, 2, hasController);\r
+  }\r
+  catch(Exception e) {\r
+    throw(e);\r
+  }\r
+  out << "  end component; " << endl << endl;\r
 }\r
 \r
 \r