// others\r
\r
void populate(); // create parameters and interface from reference block\r
+ void generateVHDL(const QString& path) throw(Exception); // main entry to generate the VHDL code \r
+\r
void parametersValidation(QList<AbstractBlock *> *checkedBlocks, QList<AbstractBlock*>* blocksToConfigure);\r
\r
QString getReferenceXmlFile();\r
*/\r
void shiftRightPattern(const QMap<AbstractInterface*, QList<char>* >& pattern, int offset);\r
\r
+ void generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception); // generates comments from <comments> element\r
+ void generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception); // generates libraries from <libraries> element\r
+ void generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception); // generate the architecture using <architecture> element\r
+ void generateController(QTextStream& out) throw(Exception); // generate the wishbone controller of the block\r
+ void generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController=false) throw(Exception); // generate the entity/compo body using reference\r
+\r
QMap<AbstractInterface*, QList<char>* > consumptionPattern;\r
QMap<AbstractInterface*, QString > admittanceCyclic; // the admittance expressed as prologue-cyclic part-epilogue, deduced from admittance\r
QMap<AbstractInterface*, QList<char>* > admittance; // the admittance taking into account nb exec.\r