finished testbench generation

[blast.git] / DelayInputModifier.cpp

diff --git a/DelayInputModifier.cpp b/DelayInputModifier.cpp
index e035c388fde9c80836c8421d5c53812510e1a388..242547c1e05ee9d854adfc772cb73b92253afa39 100644 (file)
--- a/DelayInputModifier.cpp
+++ b/DelayInputModifier.cpp
@@ -1,5 +1,6 @@
 #include "DelayInputModifier.h"\r
 #include "ConnectedInterface.h"\r
+#include "AbstractBlock.h"\r
 \r
 DelayInputModifier::DelayInputModifier(ConnectedInterface *_associatedInterface, int _delayLength) : AbstractInputModifier(_associatedInterface) {\r
   setDelayLength(_delayLength);\r
@@ -20,6 +21,60 @@ QList<char>* DelayInputModifier::getModifiedInput(QList<char>* input) {
 \r
 QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {\r
 \r
+\r
+  ConnectedInterface* fromCtlIface = associatedIface->getConnectedFrom();\r
+  ConnectedInterface* fromIface = AI_TO_CON(fromCtlIface->getAssociatedIface());\r
+\r
+  ConnectedInterface* toCtlIface = associatedIface;\r
+  ConnectedInterface* toIface = AI_TO_CON(toCtlIface->getAssociatedIface());\r
+  QString toName = toIface->getOwner()->getName()+"_"+toIface->getName();\r
+  QString toCtlName = toCtlIface->getOwner()->getName()+"_"+toCtlIface->getName();\r
+  QString dm2 = "";\r
+  QString dm3 = "";\r
+  dm2.setNum(delayLength-2);\r
+  dm3.setNum(delayLength-3);\r
+  QString ret="";\r
+  int idClock = toIface->getClockDomain();\r
+  QString clkName = "ext_clk_"+QString::number(idClock);\r
+  QString resetName = "ext_reset_"+QString::number(idClock);\r
+  if (toIface->getOwner()->getParent()->isTopGroupBlock()) {\r
+    clkName = "from_clkrstgen_"+QString::number(idClock)+"_clk";\r
+    resetName ="from_clkrstgen_"+QString::number(idClock)+"_reset";\r
+  }\r
+\r
+  if (context == Architecture) {\r
+    ret = toName + "_mod_process : process("+clkName+","+resetName+")\n";\r
+    ret += "  begin\n";\r
+    ret += "    if "+resetName+" = '1' then\n";\r
+    ret += "      "+toName+"_dly     <= (others => (others => '0'));\n";\r
+    ret += "      "+toCtlName+"_dly  <= (others => '0');\n";\r
+    ret += "      "+toName+"_mod     <= (others => '0');\n";\r
+    ret += "      "+toCtlName+"_mod  <= '0';\n";\r
+    ret += "    elsif rising_edge("+clkName+") then\n";\r
+    ret += "      "+toName+"_mod <= "+toName+"_dly("+dm2+");\n";\r
+    ret += "      "+toCtlName+"_mod  <= "+toCtlName+"_dly("+dm2+");\n";\r
+    ret += "      "+toName+"_dly(0)  <= "+fromIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
+    ret += "      "+toCtlName+"_dly(0)  <= "+fromCtlIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
+    ret += "      "+toName+"_dly(1 to "+dm2+")  <= "+toName+"_dly(0 to "+dm3+");\n";\r
+    ret += "      "+toCtlName+"_dly(1 to "+dm2+")  <= "+toCtlName+"_dly(0 to "+dm3+");\n";\r
+    ret += "    end if;\n";\r
+    ret += "  end process "+toName + "_mod_process;\n";\r
+  }\r
+  else if (context == Signal) {\r
+    QString sig = toIface->toVHDL(AbstractInterface::Signal,0);\r
+    sig.replace(" : ","_mod : ");\r
+    ret = "  signal "+sig+"\n";\r
+    sig = toCtlIface->toVHDL(AbstractInterface::Signal,0);\r
+    sig.replace(" : ","_mod : ");\r
+    ret += "  signal "+sig+"\n";\r
+    QString wStr="";\r
+    wStr.setNum(toIface->getWidth());\r
+    ret += "  signal "+toName+"_dly :  vector_of_std_logic_vector"+wStr+"(0 to "+dm2+");\n";\r
+    ret += "  signal "+toCtlName+"_dly :  vector_of_std_logic(0 to "+dm2+");\n";\r
+  }\r
+\r
+  return ret;\r
+\r
 }\r
 \r
 QString DelayInputModifier::getTypeStr() {\r