start to include clkdomain converters

[blast.git] / Dispatcher.cpp

diff --git a/Dispatcher.cpp b/Dispatcher.cpp
index a9beb481f8bdb412c7cec0e5414d5fd85ba5882d..cdf8ee3b1c281ba5381bb56b605440f2de7a698e 100644 (file)
--- a/Dispatcher.cpp
+++ b/Dispatcher.cpp
@@ -2,6 +2,8 @@
 #include "Parameters.h"
 #include "MainWindow.h"
 
+#include "ExternalResource.h"
+
 #include "Graph.h"
 #include "ReferenceBlock.h"
 #include "GroupBlock.h"
@@ -69,6 +71,10 @@ GroupWidget *Dispatcher::loadProject(const QString& filename) {
     return NULL;
   }
 
+  QFileInfo info(filename);
+  params->projectPath = info.absolutePath();
+  params->projectName = info.baseName();
+  cout << "project path = " << qPrintable(params->projectPath) << endl;
   groupList.append(topGroup);
   return topGroup;
 }
@@ -171,6 +177,100 @@ void Dispatcher::changeConnectionMode(int mode){
   */
 }
 
+void Dispatcher::generateVHDL() throw(Exception) {
+  static QString fctName = "Dispatcher::generateVHDL()";
+#ifdef DEBUG_FCTNAME
+  cout << "call to " << qPrintable(fctName) << endl;
+#endif
+
+  QDir baseDir(params->projectPath);
+  QDir srcDir(params->projectPath+"/src");
+
+  if (!baseDir.exists()) {
+    cerr << "Project path " << qPrintable(params->projectPath) << " no longer exists. First, recreate it and put the project file within. Then retry to generate." << endl;
+    return;
+  }
+
+  if (srcDir.exists()) {
+    srcDir.removeRecursively();
+  }
+  baseDir.mkdir("src");
+
+  if (! baseDir.exists("testbench")) {
+    baseDir.mkdir("testbench");
+  }
+  if (! baseDir.exists("Makefile")) {
+    QFile make("/home/sdomas/Projet/Blast/code/blast/Makefile-isim");
+    QString dest = params->projectPath;
+    dest += "/Makefile";
+    make.copy(dest);
+  }
+
+  // copying external resources
+  QString dest = params->projectPath;
+  dest += "/src/";
+  try {
+    params->getGraph()->generateVHDL(dest);
+
+    QList<QString> extResources = params->getGraph()->getExternalResources();
+    foreach(QString name, extResources) {
+      cout << qPrintable(name) << endl;
+      QList<ExternalResource*> lstRes = params->searchResourceByName(name);
+      foreach(ExternalResource* res, lstRes) {
+        QFile resFile(res->getFile());
+        QFileInfo info(res->getFile());
+        QString destFile = dest+info.fileName();
+        cout << "copying " << qPrintable(res->getFile()) << " into " << qPrintable(destFile) << endl;
+        resFile.copy(destFile);
+      }
+    }
+  }
+  catch(Exception e) {
+    throw(e);
+  }
+
+  // creating parameters file
+  QString paramName = params->projectPath+"/params-isim.txt";
+  QFile paramFile(paramName);
+  if (!paramFile.open(QIODevice::WriteOnly)) {
+    throw(Exception(PROJECTPATH_NOACCESS));
+  }
+  QTextStream out(&paramFile);
+  out << "PROJECT_NAME := " << params->projectName << endl << endl;
+  out << "SRC_DIR := src" << endl;
+  out << "TB_DIR := testbench" << endl << endl;
+  out << "VHDL_SRC := ";
+  QStringList filter;
+  filter << "*.vhd" ;
+  srcDir.setNameFilters(filter);
+  QStringList listVHDL = srcDir.entryList();
+  for(int j=0;j<listVHDL.size();j++) {
+    if (j > 0) {
+      out << "\t";
+    }
+    out << "$(SRC_DIR)/" << qPrintable(listVHDL.at(j));
+    if (j != listVHDL.size()-1) {
+      out << " \\";
+    }
+    out << endl;
+  }
+  out << endl;
+  out << "VL_SRC := ${XILINX}/verilog/src/glbl.v" << endl << endl;
+  out << "TB_SRC := $(TB_DIR)/read_csv.vhd \\" << endl;
+  out << "\t$(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl;
+  out << "SIMU_EXE := $(PROJECT_NAME)_tb" << endl << endl;
+
+  paramFile.close();
+
+  QString msg = "VHDL generation completed successfully. Go to ";
+  msg += params->projectPath+" and type the following commands to launch a simulation:\n";
+  msg += "\tmake clean\n";
+  msg += "\tmake\n";
+  msg += "\tmake view\n";
+  QMessageBox::information(mainWindow,"VHDL generation", msg, QMessageBox::Ok);
+
+}
+
 void Dispatcher::generateBlockVHDL(BoxItem *item){
   static QString fctName = "Dispatcher::generateBlockVHDL()";
 #ifdef DEBUG_FCTNAME
@@ -179,10 +279,8 @@ void Dispatcher::generateBlockVHDL(BoxItem *item){
 
   if (item->getRefBlock()->isFunctionalBlock()) {
     FunctionalBlock* block = AB_TO_FUN(item->getRefBlock());
-    ReferenceBlock* ref = block->getReference();
-    BlockImplementation* impl = ref->getImplementations().at(0);
     try {
-      impl->generateVHDL(block,params->projectPath);
+      block->generateVHDL(params->projectPath);      
     }
     catch(Exception e) {
       cout << qPrintable(e.getMessage()) << endl;
@@ -559,7 +657,7 @@ GroupWidget *Dispatcher::createTopScene(){
   GroupBlock *topBlock = graph->getTopGroup();
   // creating the clkrstgen block
   ReferenceBlock* ref = params->getHiddenReferenceBlock("clkrstgen");
-  FunctionalBlock* newOne = params->getGraph()->createFunctionalBlock(topBlock, ref);
+  FunctionalBlock* newOne = params->getGraph()->createFunctionalBlock(topBlock, ref);  
   ConnectedInterface* fromIface = AI_TO_CON(topBlock->getIfaceFromName("ext_clk"));
   ConnectedInterface* toIface = AI_TO_CON(newOne->getIfaceFromName("ext_clk"));
   fromIface->connectTo(toIface);