finalized analysis with clkconvert + started testbench gen.

[blast.git] / lib / implementations / clkrstgen_impl.xml

diff --git a/lib/implementations/clkrstgen_impl.xml b/lib/implementations/clkrstgen_impl.xml
index 7e9d15a8e4b9a93c8ae5583951862d2fa3280b08..192b142894d3aaa1e132b4b1e4fb3593b3ba2ab0 100644 (file)
--- a/lib/implementations/clkrstgen_impl.xml
+++ b/lib/implementations/clkrstgen_impl.xml
@@ -2,11 +2,10 @@
 <block_impl ref_name="clkrstgen.xml" ref_md5="">
   <comments>
     <author lastname="Domas" mail="sdomas@univ-fcomte.fr" firstname="Stephane"/>
-    <date creation="2018-01-10"/>
-    <related_files list=""/>
-    <description>implementation of cljrstgen that does the connection between
-    external and internal clock and reset</description>    
-    <notes>none</notes>
+    <log creation="2018-05-02">
+    </log>
+    <notes>
+    </notes>
   </comments>
   <libraries>
     <library name="ieee">