started VHDL generation of GroupBlock

[blast.git] / AbstractBlock.cpp

diff --git a/AbstractBlock.cpp b/AbstractBlock.cpp
index 90031d9c29c3fa31adce2d82569b81b808420872..3bb808ead3a61d5491e659821b8e426424e2ae3c 100644 (file)
--- a/AbstractBlock.cpp
+++ b/AbstractBlock.cpp
@@ -4,16 +4,21 @@
 #include "AbstractInterface.h"\r
 #include "BlockParameter.h"\r
 #include "Parameters.h"\r
+#include "GroupBlock.h"\r
+#include "ConnectedInterface.h"\r
+\r
 \r
 AbstractBlock::AbstractBlock() {\r
   name = "";\r
   parent = NULL;\r
 }\r
 \r
+/*\r
 AbstractBlock::AbstractBlock(const QString& _name) {\r
   name = Parameters::normalizeName(_name);\r
   parent = NULL;\r
 }\r
+*/\r
 \r
 AbstractBlock::~AbstractBlock() {\r
 \r
@@ -54,10 +59,12 @@ bool AbstractBlock::isSourceBlock() {
 }\r
 /* NB: a generator is a block that has no data inputs\r
  * and has at least one data output.\r
+ * By the way, blokcs that have no data input/output\r
+ * (like clkrstgen) are not generators !\r
  */\r
 bool AbstractBlock::isGeneratorBlock() {\r
   if (getDataInputs().size() > 0) return false;\r
-  \r
+  if (getDataOutputs().size() == 0) return false;\r
   return true;\r
 }\r
 \r
@@ -238,4 +245,70 @@ QList<BlockParameter *> AbstractBlock::getWishboneParameters() {
 \r
 \r
 \r
+void AbstractBlock::connectClkReset() throw(Exception) {\r
+\r
+  GroupBlock* parentBlock = AB_TO_GRP(parent);\r
+\r
+  cout << "connecting clk/rst for child " << qPrintable(name) << " of " << qPrintable(parentBlock->getName()) << endl;\r
+\r
+  QList<AbstractInterface* > lstClk = getInterfaces(AbstractInterface::Input,AbstractInterface::Clock);\r
+  QList<AbstractInterface* > lstRst = getInterfaces(AbstractInterface::Input,AbstractInterface::Reset);\r
+\r
+  if ((lstClk.isEmpty()) || (lstRst.isEmpty())) {\r
+    throw(Exception(IFACE_GROUP_NOCLKRST,this));\r
+  }\r
+\r
+  ConnectedInterface* toClk = AI_TO_CON(lstClk.at(0));\r
+  ConnectedInterface* toRst = AI_TO_CON(lstRst.at(0));\r
+\r
+  ConnectedInterface* fromClk = NULL;\r
+  ConnectedInterface* fromRst = NULL;\r
+\r
+  if (parentBlock->isTop()) {\r
+    AbstractBlock* clkrstgen = parentBlock->getFunctionalBlockByName("clkrstgen");\r
+    if (clkrstgen == NULL) {\r
+      throw(Exception(IFACE_TOP_NOCLKRSTGEN,this));\r
+    }\r
+    else {\r
+      fromClk = AI_TO_CON(clkrstgen->getIfaceFromName("clk"));\r
+      fromRst = AI_TO_CON(clkrstgen->getIfaceFromName("reset"));\r
+    }\r
+  }\r
+  else {\r
+    fromClk = AI_TO_CON(parentBlock->getIfaceFromName("clk"));\r
+    fromRst = AI_TO_CON(parentBlock->getIfaceFromName("reset"));\r
+  }\r
+  if ((fromClk == NULL) || (fromRst == NULL)) {\r
+    throw(Exception(IFACE_GROUP_NOCLKRST,parentBlock));\r
+  }\r
+  else {\r
+    fromClk->connectTo(toClk);\r
+    fromRst->connectTo(toRst);\r
+  }\r
+}\r
+\r
+void AbstractBlock::generateEntity(QTextStream& out, bool hasController) throw(Exception) {\r
+\r
+  out << "entity " << name << " is" << endl;\r
+  try {\r
+    generateEntityOrComponentBody(out, 0, hasController);\r
+  }\r
+  catch(Exception e) {\r
+    throw(e);\r
+  }\r
+  out << "end entity " << name << ";" << endl << endl;\r
+}\r
+\r
+void AbstractBlock::generateComponent(QTextStream& out, bool hasController) throw(Exception) {\r
+\r
+  out << "  component " << name << " is" << endl;\r
+  try {\r
+    generateEntityOrComponentBody(out, 2, hasController);\r
+  }\r
+  catch(Exception e) {\r
+    throw(e);\r
+  }\r
+  out << "  end component " << endl << endl;\r
+}\r
+\r
 \r