finished VHDL gen. (but have to test further

[blast.git] / DelayInputModifier.cpp

diff --git a/DelayInputModifier.cpp b/DelayInputModifier.cpp
index a90695a2ecdb6737b92a547ffa527d1e86c666cd..a60d7e27a23440da0f40c862a33e892317eda7b9 100644 (file)
--- a/DelayInputModifier.cpp
+++ b/DelayInputModifier.cpp
@@ -34,23 +34,30 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {
   dm1.setNum(delayLength-1);\r
   dm2.setNum(delayLength-2);\r
   QString ret="";\r
   dm1.setNum(delayLength-1);\r
   dm2.setNum(delayLength-2);\r
   QString ret="";\r

+  QString clkName = "clk";\r
+  QString resetName = "reset";\r
+  if (toIface->getOwner()->getParent()->isTopGroupBlock()) {\r
+    clkName = "from_clkrstgen_clk";\r
+    resetName ="from_clkrstgen_reset";\r
+  }\r
+\r

   if (context == Architecture) {\r
   if (context == Architecture) {\r

-    ret = toName + "_mod_process : process(clk,reset)\n";\r
+    ret = toName + "_mod_process : process("+clkName+","+resetName+")\n";\r

     ret += "  begin\n";\r
     ret += "  begin\n";\r

-    ret += "    if reset = '1' then\n";\r
+    ret += "    if "+resetName+" = '1' then\n";\r

     ret += "      "+toName+"_dly     <= (others => (others => '0'));\n";\r
     ret += "      "+toCtlName+"_dly  <= (others => '0');\n";\r
     ret += "      "+toName+"_mod     <= (others => '0');\n";\r
     ret += "      "+toCtlName+"_mod  <= '0';\n";\r
     ret += "      "+toName+"_dly     <= (others => (others => '0'));\n";\r
     ret += "      "+toCtlName+"_dly  <= (others => '0');\n";\r
     ret += "      "+toName+"_mod     <= (others => '0');\n";\r
     ret += "      "+toCtlName+"_mod  <= '0';\n";\r

-    ret += "    elsif rising_edge(clk) then\n";\r
+    ret += "    elsif rising_edge("+clkName+") then\n";\r

     ret += "      "+toName+"_mod <= "+toName+"_dly("+dm1+");\n";\r
     ret += "      "+toCtlName+"_mod  <= "+toCtlName+"_dly("+dm1+");\n";\r
     ret += "      "+toName+"_dly(0)  <= "+fromIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
     ret += "      "+toCtlName+"_dly(0)  <= "+fromCtlIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
     ret += "      "+toName+"_dly(1 to "+dm1+")  <= "+toName+"_dly(0 to "+dm2+");\n";\r
     ret += "      "+toCtlName+"_dly(1 to "+dm1+")  <= "+toCtlName+"_dly(0 to "+dm2+");\n";\r
     ret += "      "+toName+"_mod <= "+toName+"_dly("+dm1+");\n";\r
     ret += "      "+toCtlName+"_mod  <= "+toCtlName+"_dly("+dm1+");\n";\r
     ret += "      "+toName+"_dly(0)  <= "+fromIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
     ret += "      "+toCtlName+"_dly(0)  <= "+fromCtlIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
     ret += "      "+toName+"_dly(1 to "+dm1+")  <= "+toName+"_dly(0 to "+dm2+");\n";\r
     ret += "      "+toCtlName+"_dly(1 to "+dm1+")  <= "+toCtlName+"_dly(0 to "+dm2+");\n";\r

-    ret += "    end if\n";\r
-    ret += "  end process "+toName + "_mod_process\n";\r
+    ret += "    end if;\n";\r
+    ret += "  end process "+toName + "_mod_process;\n";\r

   }\r
   else if (context == Signal) {\r
     QString sig = toIface->toVHDL(AbstractInterface::Signal,0);\r
   }\r
   else if (context == Signal) {\r
     QString sig = toIface->toVHDL(AbstractInterface::Signal,0);\r