return triggers.size();\r
}\r
\r
+QList<QString> FunctionalBlock::getExternalResources() {\r
+\r
+ BlockImplementation* impl = reference->getImplementations().at(0); // for now only take first impl available\r
+ QList<QString> list = impl->getResources();\r
+ foreach(QString s, list) {\r
+ cout << qPrintable(s) << " ";\r
+ }\r
+ cout << endl;\r
+\r
+ return list;\r
+}\r
+\r
+\r
void FunctionalBlock::generateVHDL(const QString& path) throw(Exception){\r
\r
- BlockImplementation* impl = reference->getImplementations().at(0); // for now only take first impl available\r
+ BlockImplementation* impl = reference->getImplementations().at(0); // for now only take first impl available \r
+\r
QFile implFile(impl->getXmlFile());\r
\r
// reading in into QDomDocument\r
QDomElement eltPack = nodePack.toElement();\r
QString namePack = eltPack.attribute("name","none");\r
QString usePack = eltPack.attribute("use","none");\r
- out << "use " << nameLib << "." << namePack << "." << usePack << endl;\r
+ out << "use " << nameLib << "." << namePack << "." << usePack << ";" << endl;\r
}\r
out << endl;\r
}\r
\r
out << indent << " port (" << endl;\r
\r
+ QString ports = "";\r
+ QTextStream outPorts(&ports);\r
+\r
// Generation of the clk & rst signals\r
- out << indent << " -- clk/rst" << endl;\r
+ outPorts << indent << " -- clk/rst" << endl;\r
foreach(AbstractInterface* iface, listInputs) {\r
if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
- out << indent << " " << iface->getName() << " : in std_logic;" << endl;\r
+ outPorts << indent << " " << iface->getName() << " : in std_logic;" << endl;\r
}\r
}\r
foreach(AbstractInterface* iface, listOutputs) {\r
if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
- out << indent << " " << iface->getName() << " : out std_logic;" << endl;\r
+ outPorts << indent << " " << iface->getName() << " : out std_logic;" << endl;\r
}\r
}\r
\r
if (hasController) {\r
// Generation of the wishbone signals\r
- out << indent << " -- registers r/w via wishbone" << endl;\r
+ outPorts << indent << " -- registers r/w via wishbone" << endl;\r
QList<BlockParameter*> listWB = reference->getWishboneParameters();\r
for(i=0;i<listWB.size()-1;i++) {\r
- out << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
+ outPorts << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
}\r
- out << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
+ outPorts << indent << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
}\r
\r
-\r
- int count = 0;\r
- foreach(AbstractInterface* iface, getInterfaces()) {\r
- if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++;\r
- }\r
// Generation of the data/control signals\r
\r
- int flag = 0;\r
- bool first = true;\r
-\r
- foreach(AbstractInterface* iface, listInputs) {\r
- if(iface->getPurpose() == AbstractInterface::Data) {\r
- if (first) {\r
- out << indent << " -- input data ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ QList<AbstractInterface*> listIface = getInterfaces(AbstractInterface::Input, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- input data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
}\r
}\r
- first = true;\r
- foreach(AbstractInterface* iface, listInputs) {\r
- if(iface->getPurpose() == AbstractInterface::Control) {\r
- if (first) {\r
- out << indent << " -- input control ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ listIface = getInterfaces(AbstractInterface::Input, AbstractInterface::Control);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- input control ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
}\r
}\r
- first = true;\r
- foreach(AbstractInterface* iface, listOutputs) {\r
- if(iface->getPurpose() == AbstractInterface::Data) {\r
- if (first) {\r
- out << indent << " -- output data ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ listIface = getInterfaces(AbstractInterface::Output, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- output data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
}\r
}\r
- first = true;\r
- foreach(AbstractInterface* iface, listOutputs) {\r
- if(iface->getPurpose() == AbstractInterface::Control) {\r
- if (first) {\r
- out << indent << " -- output control ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ listIface = getInterfaces(AbstractInterface::Output, AbstractInterface::Control);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- output control ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
}\r
}\r
- first = true;\r
- foreach(AbstractInterface* iface, listBidirs) {\r
- if(iface->getPurpose() == AbstractInterface::Data) {\r
- if (first) {\r
- out << indent << " -- bidirs data ports" << endl;\r
- first = false;\r
- }\r
- count--;\r
- if (count == 0) flag = AbstractInterface::NoComma;\r
- out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ listIface = getInterfaces(AbstractInterface::InOut, AbstractInterface::Data);\r
+ if (listIface.size()>0) {\r
+ outPorts << indent << " -- bidirs data ports" << endl;\r
+ foreach(AbstractInterface* iface, listIface) {\r
+ outPorts << indent << " " << iface->toVHDL(AbstractInterface::Entity, 0) << endl;\r
}\r
}\r
+\r
+ ports.chop(2);\r
+ ports += "\n";\r
+ out << ports;\r
out << indent << " );" << endl << endl;\r
\r
}\r
\r
void FunctionalBlock::generateArchitecture(QTextStream& out, QDomElement &elt ) throw(Exception) {\r
+ QRegularExpression rxPort("@\\{([a-zA-Z0-9_]+)\\}");\r
QString expr;\r
QString code = elt.text();\r
- cout << qPrintable(code) << endl;\r
+ //cout << qPrintable(code) << endl;\r
out << "architecture rtl of " << name << " is" << endl;\r
\r
QStringList listLine = code.split("\n");\r
}\r
*/\r
if(line.contains("@{")) {\r
- out << line << endl;\r
+ QMap<QString,QString> modifs;\r
+ //cout << qPrintable(line) << endl;\r
+ QRegularExpressionMatchIterator matchPort = rxPort.globalMatch(line);\r
+ while(matchPort.hasNext()) {\r
+ QRegularExpressionMatch m = matchPort.next();\r
+ QString refName = m.captured(1);\r
+ AbstractInterface* refIface = reference->getIfaceFromName(refName);\r
+ QString funName = getIfaceUserName(refIface);\r
+ if (!funName.isEmpty()) {\r
+ modifs.insert(m.captured(0),funName);\r
+ //cout << "replace " << qPrintable(refIface->getName()) << " by " << qPrintable(funIface->getName()) << endl;\r
+ }\r
+ }\r
+ QMapIterator<QString,QString> iterM(modifs);\r
+ while(iterM.hasNext()) {\r
+ iterM.next();\r
+ QString oldName = iterM.key();\r
+ QString newName = iterM.value();\r
+ line.replace(oldName,newName);\r
+ }\r
}\r
+ out << line << endl;\r
}\r
+\r
+ out << "end rtl;" << endl;\r
}\r
\r
void FunctionalBlock::generateController(QTextStream &out) throw(Exception) {\r
\r
}\r
\r
+QString FunctionalBlock::getIfaceUserName(AbstractInterface* refIface) {\r
+\r
+ if (! refIface->isReferenceInterface()) return "";\r
+\r
+ AbstractInterface* funcIface = NULL;\r
+\r
+ if (refIface->getDirection() == AbstractInterface::Input) {\r
+ foreach(AbstractInterface* iface, getInputs()) {\r
+ FunctionalInterface* fi = AI_TO_FUN(iface);\r
+ if (fi->getReference() == refIface) {\r
+ funcIface = iface;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else if (refIface->getDirection() == AbstractInterface::Output) {\r
+ foreach(AbstractInterface* iface, getOutputs()) {\r
+ FunctionalInterface* fi = AI_TO_FUN(iface);\r
+ if (fi->getReference() == refIface) {\r
+ funcIface = iface;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else if (refIface->getDirection() == AbstractInterface::InOut) {\r
+ foreach(AbstractInterface* iface, getBidirs()) {\r
+ FunctionalInterface* fi = AI_TO_FUN(iface);\r
+ if (fi->getReference() == refIface) {\r
+ funcIface = iface;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ if (funcIface == NULL) return "";\r
+\r
+ return funcIface->getName();\r
+}\r
+\r
