finished VHDL gen. (but have to test further

[blast.git] / GroupBlock.cpp

diff --git a/GroupBlock.cpp b/GroupBlock.cpp
index 66268b93e161d8bc76d0d4061b65f5f07af30e4d..5b4f34e2c9e2090c90f5d8e91ef042c7513ab1b9 100644 (file)
--- a/GroupBlock.cpp
+++ b/GroupBlock.cpp
@@ -6,6 +6,7 @@
 #include "string.h"
 #include <sstream>
 #include "Parameters.h"
 #include "string.h"
 #include <sstream>
 #include "Parameters.h"

+#include "DelayInputModifier.h"

 
 int GroupBlock::counter = 1;
 
 
 int GroupBlock::counter = 1;
 


@@ -276,11 +277,20 @@ void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) {
   }
 }
 
   }
 }
 

+QList<QString> GroupBlock::getExternalResources() {
+
+  QList<QString> list;
+  foreach(AbstractBlock* block, blocks) {
+    list.append(block->getExternalResources());
+  }
+  return list;
+}
+

 void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
 
   QString coreFile = "";
 
 void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
 
   QString coreFile = "";
 

-  coreFile = path;
+  coreFile = path;  

   coreFile.append(Parameters::normalizeName(name));
   coreFile.append(".vhd");
 
   coreFile.append(Parameters::normalizeName(name));
   coreFile.append(".vhd");
 


@@ -299,6 +309,10 @@ void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
     generateLibraries(outCore,dummyElt);
     generateEntity(outCore);
     generateArchitecture(outCore,dummyElt);
     generateLibraries(outCore,dummyElt);
     generateEntity(outCore);
     generateArchitecture(outCore,dummyElt);

+
+    foreach(AbstractBlock* block, blocks) {
+      block->generateVHDL(path);
+    }

   }
   catch(Exception err) {
     throw(err);
   }
   catch(Exception err) {
     throw(err);


@@ -429,6 +443,38 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
 
   out << "architecture rtl of " << name << " is " << endl << endl;
 
 
   out << "architecture rtl of " << name << " is " << endl << endl;
 

+  // generate type for delays, if needed.
+  QList<int> modWidth;
+  foreach(AbstractBlock* block, blocks) {
+    QList<AbstractInterface*> listCtlInputs = block->getControlInputs();
+    foreach(AbstractInterface* iface, listCtlInputs) {
+      ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+      AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+      if (modifier != NULL) {
+        ConnectedInterface* connIface = AI_TO_CON(connCtlIface->getAssociatedIface());
+        int w = connIface->getWidth();
+        if (w == -1) throw(Exception(INVALID_VALUE));
+        if (!modWidth.contains(w)) {
+          modWidth.append(w);
+        }
+      }
+    }
+  }
+  if (modWidth.size() > 0) {
+
+    out << "  -- types for modified inputs" << endl;
+    out << "  type vector_of_std_logic is array (natural range <>) of std_logic;" << endl;
+    foreach(int w, modWidth) {
+      QString mw = "";
+      mw.setNum(w);
+      QString mwm1 = "";
+      mwm1.setNum(w-1);
+      out << "  type vector_of_std_logic_vector"<< mw << " is array (natural range <>) of std_logic_vector(" << mwm1 << " downto 0);" << endl;
+    }
+    out << endl;
+  }
+
+

   // generate the components
   foreach(AbstractBlock* block, blocks) {
     try {
   // generate the components
   foreach(AbstractBlock* block, blocks) {
     try {


@@ -442,10 +488,10 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
   out << endl;
   // generate signals
   out << "  ----------------------------" << endl;
   out << endl;
   // generate signals
   out << "  ----------------------------" << endl;

-  out << "    SIGNALS" << endl;
+  out << "  --  SIGNALS" << endl;

   out << "  ----------------------------" << endl << endl;
 
   out << "  ----------------------------" << endl << endl;
 

-
+// "normal" signals

   foreach(AbstractBlock* block, blocks) {
     try {
       out << "  -- signals from output ports of " << block->getName() << endl;
   foreach(AbstractBlock* block, blocks) {
     try {
       out << "  -- signals from output ports of " << block->getName() << endl;


@@ -466,12 +512,24 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
     }
     out << endl;
   }
     }
     out << endl;
   }

+
+  // signal for modifiers

   foreach(AbstractBlock* block, blocks) {
   foreach(AbstractBlock* block, blocks) {

-    try {
-      out << "  -- signals for modified input ports of " << block->getName() << endl;
-      QList<AbstractInterface*> listInputs = block->getInputs();
-      foreach(AbstractInterface* iface, listInputs) {
-        if (iface->getPurpose() == AbstractInterface::Control) {
+    bool hasModif = false;
+    QList<AbstractInterface*> listCtlInputs = block->getControlInputs();
+
+    foreach(AbstractInterface* iface, listCtlInputs) {
+      ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+      AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+      if (modifier != NULL) {
+        hasModif = true;
+        break;
+      }
+    }
+    if (hasModif) {
+      try {
+        out << "  -- signals for modified input ports of " << block->getName() << endl;
+        foreach(AbstractInterface* iface, listCtlInputs) {

           ConnectedInterface* connCtlIface = AI_TO_CON(iface);
           AbstractInputModifier* modifier = connCtlIface->getInputModifier();
           if (modifier != NULL) {
           ConnectedInterface* connCtlIface = AI_TO_CON(iface);
           AbstractInputModifier* modifier = connCtlIface->getInputModifier();
           if (modifier != NULL) {


@@ -479,11 +537,11 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
           }
         }
       }
           }
         }
       }

+      catch(Exception e) {
+        throw(e);
+      }
+      out << endl;

     }
     }

-    catch(Exception e) {
-      throw(e);
-    }
-    out << endl;

   }
 
   out << "begin" << endl;
   }
 
   out << "begin" << endl;